3 Layout Comparison of TPS62866

Three different versions of PCB are designed and studied for thermal analysis. In the E1 version, through-hole micro vias or thermal vias are placed under the device and near the VOUT net of the inductor. In the SW net of the device and the inductor, blind vias are provided. This is obviously a performance optimized solution.

The E2 version is a cost optimized solution and hence no vias are provided under the device as well as the inductor. But the micro vias near the VOUT net of the inductor is unchanged.

In the E3 version, a trade-off between cost and performance is achieved by providing through-hole micro vias under the device even in the SW net. Blind vias are not used under the device or the inductor. Micro vias near the VOUT net of the inductor is unchanged.