Table 3-1 shows that bench test results are smaller than calculated results. The factor can make such impact is high-side FET on time. Although it is fixed once Vin and Vout are fixed in D-CAP control, non-ideal characteristic of internal circuit can make it match with calculation not precisely. Varied high side FET on time can make inductor current rise to different peak value than estimated, resulting in different output voltage ripple as well.

Figure 3-8 shows real high-side FET on time in test. Calculated high-side FET on time is about 417ns, while real test shows 410ns. Such shrink in high-side FET on time can make output voltage ripple smaller than calculated value, which matches the trend shown in Table 3-1.

Figure 3-8 Real High-Side FET on Time in Test Under 0A Loading