SLUAAT9 January   2024 UCC27201A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Start-Up Operation
  5. 2Design Considerations
  6. 3Proper Sizing of Bootstrap and VDD Capacitors
  7. 4High Power Continuous Operation
  8. 5Design Considerations
  9. 6Summary
  10. 7References

1 Start-Up Operation

To maintain proper expected operation of the power converter, one must understand the start-up sequence of the half-bridge driver especially if using a bootstrap bias for the floating high-side driver. Some designers possibly may not be aware of the timing sequence of the half-bridge driver IC unless the designers encounter issues with the converter operation. For the driver outputs to respond to the LI (low-side) and HI (high-side) inputs, the VDD voltage level must be above the rising VDD UVLO (under voltage lockout) threshold. After the VDD UVLO threshold is satisfied there is a UVLO delay time before the outputs responds to the driver inputs. There is also a UVLO on the HB (high-side) bias, so the HB bias must be well above the rising HB UVLO threshold for the HO output to respond to the HI input. The HB UVLO circuit also has a delay time before the HO (high-side driver output) responds to the HI input.

To better understand the concerns of driver startup in a bidirectional DC-DC converter, we look at the driver start-up sequence in a standard DC-DC synchronous buck starting at 0V on the output as a reference.

The preferred startup sequence for the driver is to have VDD rise and well above the UVLO threshold before the PWM signals for LI and HI start. Since there is a UVLO delay on VDD, we recommend a delay of 10us or longer from VDD rising to the PWM signal start. In the typical synchronous buck with the output starting at 0V, there is a path from VDD through the boot diode to HB to charge the HB capacitor. This capacitor is charged when HS is close to ground which is the case at startup since VOUT is 0V and the output inductor provides a path from HS to ground, refer to Figure 1-1. The HB to HS capacitor charges at the same time that VDD is rising due to this path to the output which starts at 0V. Once VDD is above the UVLO threshold and HB-HS is above the UVLO threshold for 5-10us for most typical half-bridge drivers, the LO and HO outputs respond to the LI and HI inputs. Regarding the HB floating bias bootstrap circuit, the forward current in the driver boot diode typically has low forward current assuming the VDD rise time dV/dt is low which is the case in most systems. Typically, the bootstrap capacitor is fully charged before switching begins in the driver and power stage. Figure 1-2 shows this sequencing as well as how HS voltage rises to reverse bias the bootstrap diode.
GUID-20240111-SS0I-JT3J-DBD8-NBHTFQ4QBFMX-low.svg Figure 1-1 Simplified Synchronous Buck Showing Boot Capacitor Charging Path
GUID-20240111-SS0I-N27P-W6X0-TCKDHNJJD0HW-low.svg Figure 1-2 Synchronous Buck Timing Diagram

With bidirectional DC-DC converters many applications have multi-phase synchronous buck-boost to support high current outputs. A common practice to increase efficiency at lighter loads is to disable phases as the output current/power is decreased. Figure 1-3 illustrates a 2-phase configuration with one phase active and one in the inactive state. In practice there can be additional phases in the converter. In this case there is 12V on the output supplied by the active phase and the 2nd phase has the 12V output on the power stage switch node. On the inactive phase, the driver IC HS pin is at 12V which prevents the boot capacitor from charging assuming VDD is 12V or less. When the inactive phase starts switching the 1st LI input turns on the low side FET providing the charging path for the boot capacitor current (IHB) through the boot diode. Also, negative inductor current starts flowing from the 12V output through the low side FET as well. With 12V applied to the boot diode anode and high dV/dt on the HS pin, there is high initial boot diode forward current flowing. In many applications this can exceed 10A and significantly higher depending on the driver IC boot diode dynamic resistance. If the PWM pulses to the idle phase are enabled such that there is a short initial LO pulse, the forward current in the boot diode can be very high at the time the low side turns off. With 12V on the converter output there is negative current ramping in the output inductor when LO turns off. This negative inductor current results in the switch node transitioning high and clamping to the 48V input. This forces off the boot diode with high forward current flowing which results in potentially high reverse current in the boot diode. This reverse recovery stress can damage the internal boot diode.

GUID-20240111-SS0I-DZNH-WRXV-1XDTDN0FM6GG-low.svg Figure 1-3 Multi-Phase Synchronous Buck-Boost HB Capacitor and Inductor Current Paths
GUID-20240111-SS0I-THNZ-LML0-LCRWKDCXVZL5-low.svg Figure 1-4 Timing Diagram of Inactive Phase Start-Up