BIAS SUPPLY (VCC) |
|
VCC current, disabled |
SS = 0 V |
|
1 |
1.5 |
mA |
|
VCC current, enabled |
SS = 5 V, CGD1 = CGD2 = 1 nF |
2.5 |
5 |
7.5 |
|
VCC current, UVLO |
VCC = 9 V |
|
100 |
400 |
μA |
VUVLO |
UVLO turn-on threshold |
Measured at VCC rising |
9.9 |
10.5 |
11.1 |
V |
UVLO turn-off threshold |
Measured at VCC falling |
8.9 |
9.5 |
10.1 |
UVLO hysteresis |
Measured at VCC |
0.7 |
1 |
1.3 |
VOVP |
OVP turn-off threshold |
Measured at VCC rising |
18 |
20 |
22 |
OVP turn-on threshold |
Measured at VCC falling |
16 |
18 |
20 |
OVP hysteresis |
Measured at VCC |
1.5 |
2 |
2.5 |
DEAD TIME (DT) |
TDT |
Dead time |
RDT = 16.9 kΩ |
390 |
420 |
450 |
ns |
OSCILLATOR |
FSW(min) |
Minimum switching frequency at GD1, GD2 |
–40°C to 125°C |
40.04 |
41.70 |
43.36 |
kHz |
–20°C to 105°C |
40.45 |
41.70 |
42.95 |
KICO |
Switching frequency gain/I (RT) |
RRT = 4.7 kΩ, IRT = 0 to 1 mA |
60 |
80 |
100 |
Hz/μA |
|
GD1, GD2 on time mismatching |
|
–50 |
|
50 |
ns |
FSW_BM |
Switching frequency starting burst mode |
SS = 5 V |
300 |
350 |
400 |
kHz |
Switching frequency to come out of burst mode |
SS = 5 V |
280 |
330 |
380 |
FSW(start) |
Switching frequency at soft-start |
–40°C to 125°C |
122 |
142.5 |
162 |
–20°C to 105°C |
125 |
142.5 |
160 |
EXTERNAL DISABLE/SOFT START |
|
Enable threshold |
Measure at SS rising |
1.1 |
1.2 |
1.3 |
V |
|
Disable threshold |
Measured at SS falling |
0.85 |
1 |
1.1 |
|
Disable hysteresis |
Measured at SS |
0.15 |
|
0.35 |
|
Disable prop. delay |
Measured between SS (falling) and GD2 (falling) |
250 |
500 |
750 |
ns |
ISS |
Source current on ISS pin |
VSS = 0.5 V |
–225 |
–175 |
–125 |
μA |
Source current on ISS pin |
VSS = 1.35 V |
–5.5 |
–5 |
–4.5 |
PEAK CURRENT LIMIT |
VOC1(off) |
Level 1 overcurrent threshold – VOC rising |
|
0.9 |
1 |
1.1 |
V |
VOC2(off) |
Level 2 overcurrent latch threshold – VOC rising |
|
1.8 |
2.0 |
2.2 |
VOC1(on) |
Level 1 overcurrent threshold – VOC falling |
|
0.5 |
0.6 |
0.7 |
Td_OC |
Propagation delay |
|
60 |
200 |
500 |
ns |
IOC |
OC bias current |
VOC = 0.8 V |
–200 |
|
200 |
nA |
GATE DRIVE |
|
GD1, GD2 output voltage high |
IGD1, IGD2 = −20 mA |
9 |
|
11 |
V |
|
GD1, GD2 on resistance high |
IGD1, IGD2 = −20 mA |
|
12 |
30 |
Ω |
|
GD1, GD2 output voltage low |
IGD1, IGD2 = 20 mA |
|
0.08 |
0.2 |
V |
|
GD1, GD2 on resistance low |
IGD1, IGD2 = 20 mA |
|
4 |
10 |
Ω |
|
Rise time GDx |
1 V to 9 V, CLOAD = 1 nF |
|
18 |
35 |
ns |
|
Fall time GDx |
9 V to 1 V, CLOAD = 1 nF |
|
12 |
25 |
|
GD1, GD2 output voltage during UVLO |
VCC = 6 V, IGD1, IGD2 = 1.2 mA |
0.5 |
|
1.75 |
V |
THERMAL SHUTDOWN |
|
Thermal shutdown threshold |
|
|
160 |
|
°C |
|
Thermal shutdown recovery threshold |
|
|
140 |
|