SLVAEP4 October   2023 BQ79600-Q1 , BQ79612-Q1 , BQ79614-Q1 , BQ79616 , BQ79616-Q1 , BQ79652-Q1 , BQ79654-Q1 , BQ79656-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. Introduction
  5. Receiver Topology and Common Mode Voltages
  6. Signal Integrity Requirements
    1. 3.1 Receiver Timing Requirements
    2. 3.2 Receiver Threshold Requirements
  7. Debug Fault Registers
  8. Isolation Types
    1. 5.1 Transformer Isolation
    2. 5.2 Capacitor Only Isolation
    3. 5.3 Capacitor and Choke Isolation
  9. Mixed Isolation Circuits using bq79600-Q1
  10. Ring Architecture
  11. Noise Immunity and Emissions
  12. Daisy Chain Cable Selection
  13. 10References

Introduction

The daisy chain communication interface on the bq7961X family of devices is a proprietary protocol developed by Texas Instruments. It is designed using differential signaling to minimize Electro-Magnetic Susceptibility (EMS) and strengthen Bulk Current Injection (BCI) immunity. The differential communication transmits complement data on the COM*P and COM*N pins, respectively. This interface is bi-directional and half duplex, and, therefore, has a transmitter (TX) and receiver (RX) on the COMH (high -side) and COML (low-side) interfaces.

The device supports the use of transformers or capacitors to electrically isolate the signals between devices in the stack. There are configurations where the devices are physically located on the same board or located in entirely separate packs connected with twisted pair wiring. For applications that have multiple devices on the same PCB, a single capacitor is connected between the COMH/L pins of the devices. For extremely noisy environments and stringent EMI/EMC requirements, additional filtering may be necessary. For devices that are separated by cabling, additional isolation components are used.

GUID-BDCEF4C9-0D57-41E4-AA97-DFD358CB111F-low.gif Figure 1-1 Daisy Chain Byte Level Definition
GUID-6FA4A867-A644-4ADA-8D37-68136AF6F608-low.gif Figure 1-2 Communication Tones
GUID-353D630C-7835-4F0E-A95F-EFE1697B04D8-low.gif Figure 1-3 Daisy Chain Bit Level Definition