SLVAFH0 December   2023 CSD13201W10 , CSD13302W , CSD13303W1015 , CSD13306W , CSD13380F3 , CSD13381F4 , CSD13383F4 , CSD13385F5 , CSD15380F3 , CSD17381F4 , CSD17382F4 , CSD17483F4 , CSD17484F4 , CSD17585F5 , CSD18541F5 , CSD22202W15 , CSD22204W , CSD22205L , CSD22206W , CSD23202W10 , CSD23203W , CSD23280F3 , CSD23285F5 , CSD23381F4 , CSD23382F4 , CSD25202W15 , CSD25211W1015 , CSD25213W10 , CSD25304W1015 , CSD25480F3 , CSD25481F4 , CSD25483F4 , CSD25484F4 , CSD25485F5 , CSD25501F3 , CSD75207W15 , CSD75208W1015 , CSD83325L , CSD85302L , CSD86311W1723 , CSD87501L

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Solving Assembly Issues with Chip Scale Power MOSFETs
  5. 2Land Grid Array (LGA) MOSFET Packaging Technology
  6. 3Wafer Level Chip Scale Packaging Technology
  7. 4Common Issues
  8. 5Best Practices
  9. 6Considerations When There are Problems
    1. 6.1 Tilted or Misaligned Packages
    2. 6.2 Solder Balls, Poor, or no Solder
    3. 6.3 Chipped or Cracked Devices
  10. 7Summary
  11. 8References

5 Best Practices

Before starting a new design, the following documents provide detailed information, from PCB pad design to IR reflow profiles, required for PCB assembly of TI LGA and WLCSP FETs: FemtoFET™ Surface Mount Guide and AN-1112 DSBGA Wafer Level Chip Scale Package. Because of their construction, a silicon die (no plastic over molding, wire bonds or lead frame) with metalized or solder-bumped pads, care must be taken during the assembly process. When customers report an assembly problem, the first question to ask is did they follow TI’s recommended PCB layout and stencil patterns included in the MOSFET data sheets? These have been optimized by TI through design of experiment (DOE) studies, used to qualify the packages, and are key to successful PCB assembly