The LM5177 high-side and low-side gate drivers incorporate short propagation delays, frequency depended dead-time control, and low-impedance output stages capable of delivering large peak currents with very fast rise and fall times to facilitate rapid turn-on and turn-off transitions of the external power MOSFETs.

Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance, whether it be series gate inductance that resonates with MOSFET gate capacitance or common source inductance (common to gate and power loops) that provides a negative feedback component opposing the gate drive command, and thereby increasing MOSFET switching times.

The PCB trace capacitance for the gate drive is normally negligible, so it will be ignored here. Figure 2-4 shows the equivalent gate-drive circuit. R_Trace1 is the PCB drive trace resistance, R_Trace2 is the drive return trace resistance, L_Trace1 is the drive trace stray inductance, L_Trace2 is the return path inductance and C_iss is the MOSFET gate input capacitance. The trace resistances and inductance can cause gate signal delays; therefore, it’s best to keep the drive and return traces as short as possible.

Given board area limitations, it is often not possible to place the driver very close to the MOSFET. Even if the MOSFET is not very close, it is possible to make R_Trace1 and R_Trace2 <1 Ω in most designs. However, L_Trace1 and L_Trace2 can become significant if the trace routing is poor.An inductance of just a few nanohenries may resonate wildly with the MOSFET gate capacitance and create gate voltage ringing, as shown in Figure 2-5. If the magnitude of the ringing exceeds the MOSFET gate threshold voltage, Vth, it will cause unwanted extra switching action and result in severe switching losses inside the MOSFETs. Also, the negative peak can exceed the allowed gate signal level of the MOSFET.

How can you minimize the gate-drive inductance? According to physics, the gate-drive inductance is proportional to the spatial area enclosed by the drive current loop, which is the area defined by the actual drive and return traces. Minimizing the spatial area of the drive current loop needs to be your main focus in routing the MOSFET drive and return paths.

Assume that the drive is at point A and the MOSFET is at point B on the PCB; the drive trace must be routed from point A to point B and return back to point A. Also assume that a straight trace from A to B is not possible because other components are in the way. Figure 2-6 shows two different routing patterns. Obviously, option Number 2 encloses a minimal spatial area and thus produces the least inductance, even though the total trace length is almost the same as option Number 1. This example clearly shows that the optimal routing is to place the drive and return traces closely side by side for the entire distance between the driver and the MOSFET.

Again, given board area limitations, sometimes there is no space to place the pair of drive and return traces side by side on the same layer. A design is to route the return trace in the shadow of the drive trace on the adjacent layer, as shown in Figure 2-7, where the drive trace runs from point A (Drive) on Layer 1 to point B (MOSFET), and takes the via hole to Layer 2, and runs back to point A in the shadow of the drive trace. In this way, the drive and return traces basically run closely side by side in the vertical direction, minimizing the spatial area enclosed by the signal loop.

In LM5177, connections from the gate driver outputs, HO1 and HO2, to the respective gates of the high-side MOSFETs must be as short as possible to reduce series parasitic inductance. Route HO1 and HO2 and SW1 and SW2 gate traces as a differential pair from the device pin to the high-side MOSFET, taking advantage of flux cancellation by reducing the loop area.

Connections from gate driver outputs, LO1 and LO2, to the respective gates of the low-side MOSFETs must be as short as possible to reduce series parasitic inductance. Route LO1 and LO2, and PGND traces as a differential pair from the device pin to the low-side MOSFET, taking advantage of flux cancellation by reducing the loop area.

Minimize the current loop paths from the VCC, HB1, and HB2 pins through their respective capacitors as these provide the high instantaneous current.