SLVSAU0G May   2011  – December 2015 TPD4S014

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, EN, ACK, D+, D-, ID Pins
    6. 6.6 Electrical Characteristics OVP Circuits
    7. 6.7 Supply Current Consumption
    8. 6.8 Thermal Shutdown Feature
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage Protection at VBUS up to 28 V DC
      2. 7.3.2 Low RON nFET Switch
      3. 7.3.3 ESD Performance D+/D-/ID/VBUS Pins
      4. 7.3.4 Overvoltage and Undervoltage Lockout Features
      5. 7.3.5 Capacitance TVS ESD Clamp for USB2.0 Hi-Speed Data Rate
      6. 7.3.6 Start-up Delay
      7. 7.3.7 OVP Glitch Immunity
      8. 7.3.8 Integrated Input Enable and Status Output Signal
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 For Non-OTG USB Systems
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 For OTG USB Systems
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7 Detailed Description

7.1 Overview

The TPD4S014 provides a single-chip protection solution for USB charger interfaces. The VBUS line is tolerant up to 28 V DC. A Low RON nFET switch is used to disconnect the downstream circuits in case of a fault condition. At power-up, when the voltage on VBUS is rising, the switch will close 17 ms after the input crosses the under voltage threshold, thereby making power available to the downstream circuits. The TPD4S014 also has an ACK output, which de-asserts to alert the system a fault has occurred. The TPD4S014 offers 4 channel ESD clamps for D+, D-, ID, and VBUS pins that provide IEC61000-4-2 level 4 ESD protection. This eliminates the need for external TVS clamp circuits in the application.

7.2 Functional Block Diagram

TPD4S014 cir_sch_lvsau0.gif

7.3 Feature Description

7.3.1 Input Voltage Protection at VBUS up to 28 V DC

When the input voltage rises above VOVP, or drops below the VUVLO, the internal VBUS switch is turned off, removing power to the application. The ACK signal is de-asserted when a fault condition is detected. If the fault was an over voltage event, the VBUS nFET switch turns on 8 ms (tREC) after the input voltage returns below VOVP – VHYS_OVP and remains above VUVLO. If the fault was an under voltage event, the switch turns on 17 ms after the voltage returns above VUVLO+ (similar to start up). When the switch turns on, the ACK is asserted once again.

7.3.2 Low RON nFET Switch

The nFET switch has a total on resistance (RON) of 151 mΩ. This equates to a voltage drop of 302 mV when charging at the maximum 2.0 A current level. Such low RON helps provide maximum potential to the system as provided by an external charger.

7.3.3 ESD Performance D+/D–/ID/VBUS Pins

The D+, D–, ID, and VBUS pins can withstand ESD events up to ±15-kV contact and air-gap. An ESD clamp diverts the current to ground.

7.3.4 Overvoltage and Undervoltage Lockout Features

The over voltage and under voltage lockout feature ensures that if there is a fault condition at the VBUS line, the TPD4S014 is able to isolate the VBUS line and protect the internal circuitry from damage. Due to the body diode of the nFET switch, if there is a short to ground on VBUS the system is expected to limit the current to VBUSOUT.

7.3.5 Capacitance TVS ESD Clamp for USB2.0 Hi-Speed Data Rate

The D+/D– ESD protection pins have low capacitance so there is no significant impact to the signal integrity of the USB 2.0 Hi-Speed data rate.

7.3.6 Start-up Delay

Upon startup, TPD4S014 has a built in startup delay. An internal oscillator controls a charge pump to control the turn-on delay (tON) of the internal nFET switch. The internal oscillator controls the timers that enable the turn-on of the charge pump and sets the state of the open-drain ACK output. If VBUS < VUVLO or if VBUS > VOVLO, the internal oscillator remains off, thus disabling the charge pump. At any time, if VBUS drops below VUVLO or rises above VOVLO, ACK is released and the nFET switch is disabled.

7.3.7 OVP Glitch Immunity

A 17 ms deglitch time has been introduced into the turn on sequence to ensure that the input supply has stabilized before turning the nFET switch ON. Noise on the VBUS line could turn ON the nFET switch when the fault condition is still active. To avoid this, OVP glitch immunity allows noise on the VBUS line to be rejected. Such a glitch protection circuitry is also introduced in the turn off sequence in order to prevent the switch from turning off for voltage transients. The glitch protection circuitry integrates the glitch over time, allowing the OVP circuitry to trigger faster for larger voltage excursions above the OVP threshold and slower for shorter excursions.

7.3.8 Integrated Input Enable and Status Output Signal

External control of the nFET switch is provided by an active low EN pin. An ACK pin provides output logic to acknowledge VBUS is between UVLO and OVP by asserting low.

7.3.9 Thermal Shutdown

When the device is ON, current flowing through the device will cause the device to heat up. Overheating can lead to permanent damage to the device. To prevent this, an over temperature protection has been designed into the device. Whenever the junction temperature exceeds 145ºC, the switch will turn off, thereby limiting the temperature. The ACK signal will be asserted for an over temperature event. Once the device cools down to below 120ºC the ACK signal will be de-asserted, and the switch will turn on if the EN is active and the VBUS voltage is within the UVLO and OVP thresholds. While the over temperature protection in the device will not kick-in unless the die temperature reaches 145ºC, it is generally recommended that care is taken to keep the junction temperature below 125 ºC. Operation of the device above 125 ºC for extended periods of time can affect the long-term reliability of the part.

The junction temperature of the device can be calculated using below formula:

Equation 1. TPD4S014 Eqn1_lvsau0.gif

where

  • TJ = Junction temperature
  • Ta = Ambient temperature
  • θJA = Thermal resistance
  • PD = Power dissipated in device
Equation 2. TPD4S014 Eqn2_lvsau0.gif

where

  • I = Current through device
RON = Max on resistance of device

Example

At 2-A continuous current power dissipation is given by:

TPD4S014 Eqn3_lvsau0.gif

If the ambient temperature is about 60°C the junction temperature will be:

TPD4S014 Eqn4_lvsau0.gif

This implies that, at an ambient temperature of 60ºC, TPD4S014 can pass a continuous 2 A without sustaining damage. Conversely, the above calculation can also be used to calculate the total continuous current the TPD4S014 can handle at any given temperature.

7.4 Device Functional Modes

Table 1 is the function table for TPD4S014.

Table 1. Function Table

OTP UVLO OVLO EN SW ACK
X H X X OFF H
X X H X OFF H
L L L H OFF L
L L L L ON L
H X X X OFF H
OTP = Over temperature protection circuit active
UVLO = Under voltage lock-out circuit active
OVLO = Over voltage lock-out circuit active
SW = Load switch
CP = Charge pump
X = Don’t Care
H = True
L = False