SLVU097B October   2003  – October 2021 TPS54350

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification Summary
    3. 1.3 Modifications
      1. 1.3.1 Output Voltage Setpoint
      2. 1.3.2 Switching Frequency
      3. 1.3.3 Input Filter
      4. 1.3.4 UVLO Programming
      5. 1.3.5 Synchronization
      6. 1.3.6 Power Good
      7. 1.3.7 Synchronous Low-Side FET
      8. 1.3.8 Optional Output Filtering
  3. 2Test Setup and Results
    1. 2.1  Input/Output Connections
    2. 2.2  Efficiency
    3. 2.3  Power Dissipation
    4. 2.4  Output Voltage Regulation
    5. 2.5  Load Transients
    6. 2.6  Loop Characteristic
    7. 2.7  Output Voltage Ripple
    8. 2.8  Input Voltage Ripple
    9. 2.9  Gate Drive
    10. 2.10 Powering Up and Down
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Bill of Materials
  6. 5Revision History

2.2 Efficiency

The TPS54350EVM−235 efficiency peaks at load current of approximately 1 A and VI of 6 V, and then decreases as the load current increases towards full load. For higher input voltages, quiescent losses are greater and the efficiency peaks under full load conditions. It is important to consider that this design is optimized for small size and flexibility and does not reflect the high efficiencies that are possible for specific applications using the TPS54350. Figure 2-2 shows the efficiency for the TPS54350 at an ambient temperature of 250°C. The efficiency is lower at higher ambient temperatures, due to temperature variation in the drain-to-source resistance of the MOSFETs. The efficiency is slightly lower at 500 kHz than at lower switching frequencies due to the gate and switching losses in the MOSFETs.

GUID-20210929-SS0I-TXKR-V0KN-JQPHHMB225JH-low.gif Figure 2-2 Measured Efficiency