SLVUA33A March   2014  – July 2021 TPS563900

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification Summary
    3. 1.3 Modifications
      1. 1.3.1 Output Voltage Setpoint
      2. 1.3.2 Slow-Start Time
      3. 1.3.3 Adjustable UVLO
  3. 2Test Setup and Results
    1. 2.1 Input/Output Connections
    2. 2.2 Efficiency
    3. 2.3 Output Voltage Load Regulation
    4. 2.4 Output Voltage Line Regulation
    5. 2.5 Load Transients
    6. 2.6 Loop Characteristics
    7. 2.7 Output Voltage Ripple
    8. 2.8 Powering Up
    9. 2.9 Shutting Down
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
    3. 4.3 Reference
  6. 5Revision History

3.1 Layout

The board layout for the TPS563900EVM-574 is shown in Figure 3-1 through Figure 3-5. The top-side layer of the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz. copper.

The top layer contains the main power traces for VIN, VOUT1, VOUT2 and switching nodes. Also on the top layer are connections for the remaining pins of the TPS563900 and a large area filled with ground. The internal layer-1 is dedicated to a power ground plane. The internal layer-2 contains additional VIN, VOUT1 and VOUT2 copper fill areas as well as signal routing traces. The bottom layer contains a power ground plane only. The top-side ground traces are connected to the bottom and internal ground planes with multiple vias placed around the board .

The input decoupling capacitors (C1 and C2) and V7V LDO output capacitor C3 and bootstrap capacitors (C9 and C19) are all located as close to the IC as possible. Additionally, the voltage set point resistor divider components are kept close to the IC. The voltage divider network ties to the output voltages at the point of regulation, the copper VOUT1 and VOUT2 traces on the internal layer-2 near the J3 and J4 output connectors respectively. For the TPS563900, an additional input bulk capacitor may be required, depending on the EVM connection to the input supply.

Figure 3-1 TPS563900EVM-574 Top-Side Assembly
Figure 3-3 TPS563900EVM-574 Internal Layer-1 Layout
Figure 3-5 TPS563900EVM-574 Bottom-Side Layout
Figure 3-2 TPS563900EVM-574 Top-Side Layout
Figure 3-4 TPS563900EVM-574 Internal Layer-2 Layout