SLVUC17 August   2021 TPS7H2211-SP

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Default Board Configuration
    2. 1.2 Alternate Board Configurations
  3. 2EVM Connectors and Test Points
  4. 3Test Results
    1. 3.1 Default Configuration Results
    2. 3.2 Parallel Configuration Results
  5. 4Board Layout
  6. 5Schematic
    1. 5.1 Default Configuration Schematic
    2. 5.2 Parallel Configuration Schematic
  7. 6Bill of Materials (BOM)
    1. 6.1 Default Configuration BOM
    2. 6.2 Parallel Configuration BOM

2 EVM Connectors and Test Points

GUID-DAFEA57F-E862-4A73-A08D-14A8D99193B7-low.png Figure 2-1 TPS7H2211EVM-CVAL 3D Rendering (Top)
Table 2-1 Summary of Connectors and Test Points
Reference Designator Function
J3, J6 (pins 3& 4)

VIN

 Input Voltage and Current for Board

J8, J6 (pins 1 & 2)

GND
J4, J15 (pins 3& 4)

VOUT

Output Voltage and Current for Board
J18, J15 (pins 1 & 2)

GND
J1, TP1, TP3 Input Voltage Test Points
J2, TP2, TP4 Output Voltage Test Points
TP7, TP8, TP10, TP11 Ground Test Points
TP5 Soft Start Test Point
TP6 Enable Test Point
TP9 OVP Test Point