SLVUCD1 May   2022 TPS65219

 

  1.   Abstract
  2.   Trademarks
  3. 1Caution
  4. 2Introduction
  5. 3Requirements
    1. 3.1 Hardware
    2. 3.2 Software
  6. 4TPS65219 Resources Overview
  7. 5EVM Configuration
    1. 5.1 Default EVM Configuration
    2. 5.2 Configuration Headers
    3. 5.3 Test Points
  8. 6Graphical User Interface (GUI)
    1. 6.1 Using USB2ANY With the TPS65219EVM
  9. 7Schematics, PCB Layouts, and Bill of Materials
    1. 7.1 TPS65219EVM Schematic
    2. 7.2 TPS65219EVM PCB Layers
    3. 7.3 Bill of Materials

4 TPS65219 Resources Overview

The TPS65219 PMIC has multiple analog and digital resources that can be configured to power different processors, FPGAs and SoCs. Table 4-1 and Table 4-2 summarize some of the key electrical spec specification for the analog rails, the possible supply configurations and programmable features for each regulator.

Table 4-1 TPS65219 Power Resources
Buck1 Buck2/3 LDO1/2 LDO3/4
Input Voltage Range 2.5V to 5.5V 2.5V to 5.5V 1.5V to 5.5V 2.5V to 5.5V
Output Voltage Range 0.6V to 3.4V 0.6V to 3.4V 0.6V to 3.4V 1.2V to 3.3V
Operating Current Maximum of 3.5A Maximum of 2A 400mA 300mA
Current Limiting 5.7A to 6.9A 3.9A to 4.7A 600A to 900mA 400A to 900mA
Status Monitoring UV, NEG_OC, OC, SCG, RV UV, NEG_OC, OC, SCG, RV UV, OC, SCG, RV UV, OC, SCG, RV
Rail Configuration Buck Converter Buck Converter LDO; load switch; bypass-mode LDO; load switch
Short-Circuit Threshold (SCG) 220mV to 300mV 220mV to 300mV 220mV to 300mV 220mV to 300mV

TPS65219 Multi function Pins

TPS65219 has three multi-function-pins that can be configured depending on functional use. Table 4-2 shows the functions available for each of these pins as well as how these functions are configured and operated.

Note: Only one of the following pins, MODE/RESET or MODE/STBY, may be configured as MODE. If both are configured as MODE, MODE/RESET will take priority and MODE/STBY will be ignored.

Table 4-2 TPS65219 Multi function Pins
Pin Name Pin Configuration Operation

VSEL_SD/VSEL_DDR

 VSEL_SD

SD-card-IO-voltage selection

 Trigger voltage change between 1.8V and register-based VLDO1 or VLDO2. Polarity is configurable.
VSEL_DDR

DDR-voltage selection

 Hard-wired pull-up, pull-down, or floating. Sets VBUCK3 to 1.35V, 1.2V or register-based VBUCK3. Level-sensitive.
MODE/RESET MODE

Forces Buck converters into PWM or auto-entry in PFM-mode

 Connected to SoC or hard-wired pull-up/down. Level-sensitive.
RESET

Forces a WARM or COLD reset.

Connected to SoC.

WARM reset: reset output voltages to default

COLD reset: sequence down all enabled rails and power up again

Edge-sensitive.
MODE/STBY MODE

Forces Buck converters into PWM or auto-entry in PFM-mode

 Pin-status determines the switching mode of the buck converters. Assert pin low for longer than tDEGLITCH_MFP to force buck regulators into PWM-mode. I2C selection also available by writing to MODE_I2C_CTRL in MFP_1_CONFIG register.
STBY

Low power mode

 Disables selected rails. Assert pin low for longer than Both MODE and STBY can be combined. Level sensitive.