SLVUCM0 august   2023 TPS65219

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521908 Sequence and Power Block Diagram
  6. 3EEPROM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Multi PMIC Config

2.1 TPS6521908 Sequence and Power Block Diagram

GUID-20230123-SS0I-G3K8-F7LF-LBZSQ904CVNP-low.svg Figure 2-1 TPS6521908 Example Power Block Diagram
GUID-20230123-SS0I-4DRT-MZJ9-2FJ9VM0GMHSV-low.svg Figure 2-2 TPS6521908 Power-Up Sequence
GUID-20230123-SS0I-BCD1-09DW-ZTV42GSXQR1H-low.svg Figure 2-3 TPS6521908 Power-Down Sequence