SLVUCS0 july   2023 TPS552872 , TPS552872-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Modification
    2. 2.2 Connector and Test Point Descriptions
    3. 2.3 Jumper Configuration
      1. 2.3.1 JP1 (ENABLE)
      2. 2.3.2 JP5 (SYNC)
      3. 2.3.3 JP6 (MODE)
      4. 2.3.4 JP7 (EXTVCC)
    4. 2.4 Test Procedure
  9. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials
  10. 4Additional Information
    1.     Trademarks

PCB Layouts

Figure 4-2 through Figure 4-5 illustrate the EVM board layouts.

GUID-20230719-SS0I-ZMHT-QHMW-F6SXZ50CTFN1-low.svg Figure 3-2 TPS552872EVM-029 Top-Side Layout
GUID-20230719-SS0I-NVDG-8VP7-V3KVZDWRKRJL-low.svg Figure 3-3 TPS552872EVM-029 Inner Layer 1
GUID-20230719-SS0I-7CDH-SCQP-J70VLL9H0L5X-low.svg Figure 3-4 TPS552872EVM-029 Inner Layer 2
GUID-20230719-SS0I-PPNL-MV2C-2NWGQSZG9QQB-low.svg Figure 3-5 TPS552872EVM-029 Bottom-Side Layout