SLVUCT9 January   2024

 

  1.   1
  2.   Description
  3.   Features
  4.   Trademarks
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Alternate Board Configurations
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Important Usage Notes
    3. 2.3 Connector Descriptions
  7. 3Implementation Results
    1. 3.1 Default Configuration Results
    2. 3.2 Sequence UP and DOWN Thresholds
    3. 3.3 Delay Timer
    4. 3.4 Regulation Timer
    5. 3.5 Disabled Channels
    6. 3.6 Externally Induced System RESET
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  9. 5Compliance Information
    1. 5.1 Compliance and Certifications
  10. 6Additional Information
    1. 6.1 Known Hardware Issues
  11. 7Related Documentation
  12. 8Revision History

2.3 Connector Descriptions

Primary Device

Secondary Device

Designator

Function

Designator

Function

J10

VIN_P

Power input connector for VIN of the primary device.

R42

VIN_S

0 Ohm resistor for tying VIN of the primary and secondary devices.

TP3

Test point

TP22

Test point

J5

PULL_UP1_P

 Power input connector for PULL_UP1 of the primary device.

R41

PULL_UP1_S

 0 Ohm resistor for tying PULL_UP1 of the primary and secondary devices.

TP5

Test point

TP24

Test point

J2

PULL_UP2_P

 Power input connector for PULL_UP2 of the primary device.

R38

PULL_UP2_S

 0 Ohm resistor for tying PULL_UP2 of the primary and secondary devices.

TP7

Test point

TP35

Test point

J6, J23

GND

 Power input connector for GND of the primary device.

GND power connections are shared between primary and secondary devices.

TP26, TP27, TP28, TP29, TP30, TP31, TP32, TP33

Test point

J24

VOUT1_P

Input connector for an external VOUT rail to be monitored by SENSE1 of the primary device.

J55

VOUT1_S

 Input connector for an external VOUT rail to be monitored by SENSE1 of the secondary device.

J31

GND

J62

GND

J28

SENSE1_P

Probe test point

J57

SENSE1_S

TP13

Test point

TP38

 Test point

J25

VOUT2_P

 Input connector for an external VOUT rail to be monitored by SENSE2 of the primary device.

J56

VOUT2_S

 Input connector for an external VOUT rail to be monitored by SENSE2 of the secondary device.

J32

GND

J63

GND

J29

SENSE2_P

Probe test point

J58

SENSE2_S

Probe test point

TP14

Test point

TP39

 Test point

J33

VOUT3_P

 Input connector for an external VOUT rail to be monitored by SENSE3 of the primary device.

J65

VOUT3_S

 Input connector for an external VOUT rail to be monitored by SENSE3 of the secondary device.

J39

GND

J70

GND

J37

SENSE3_P

Probe test point

J68

SENSE3_S

Probe test point

TP18

Test point

TP45

Test point

J34

VOUT4_P

 Input connector for an external VOUT rail to be monitored by SENSE4 of the primary device.

J66

VOUT4_S

 Input connector for an external VOUT rail to be monitored by SENSE4 of the secondary device.

J40

GND

J71

GND

J38

SENSE4_P

Probe test point

J69

SENSE4_S

Probe test point

TP19

Test point

TP46

Test point

TP1

EN1_P

Test point

TP20

EN1_S

 Test point

J3

Probe test point

J42

 Probe test point

J1

Output connector for EN1 of the primary device.

J41

 Output connector for EN1 of the secondary device.

J4

GND

J43

GND

TP2

EN2_P

Test point

TP21

EN2_S

 Test point

J8

Probe test point

J45

 Probe test point

J7

 Output connector for EN2 of the primary device.

J44

 Output connector for EN2 of the secondary device.

J9

GND

J46

GND

TP4

EN3_P

Test point

TP23

EN3_S

 Test point

J12

Probe test point

J48

 Probe test point

J11

 Output connector for EN3 of the primary device.

J47

 Output connector for EN3 of the secondary device.

J13

GND

J49

GND

TP8

EN4_P

Test point

TP34

EN4_S

 Test point

J18

Probe test point

J51

 Probe test point

J14

 Output connector for EN4 of the primary device.

J50

 Output connector for EN4 of the secondary device.

J22

GND

J52

GND

J15, J16, J17

DLY_TMR_P

Shunt for DLY_TMR resistor configuration of the primary device.

J53

DLY_TMR_S

 Shunt for DLY_TMR resistor configuration of the secondary device.

J19, J20, J21

REG_TMR_P

Shunt for REG_TMR resistor configuration of the primary device.

J54

REG_TMR_S

 Shunt for REG_TMR resistor configuration of the secondary device.

TP11

UP_P

Test point

TP41

UP_S

 Test point

J26

Probe test point

J60

 Probe test point

TP17

DOWNb_P

Test point

TP42

DOWNb_S

 Test point

J36

Probe test point

J61

 Probe test point

TP6

HYS_P

Test point

TP25

HYS_S

 Test point

TP15

FAULTb_P

Test point

TP43

FAULTb_S

 Test point

J30

Probe test point

J64

 Probe test point

TP16

SEQ_DONE_P

Test point

TP44

SEQ_DONE_S

 Test point

J35

Probe test point

J67

 Probe test point

TP12

PWRGD_P

Test point

TP40

PWRGD_S

 Test point

J27

Probe test point

J59

 Probe test point

TP9

VLDO_P

Test point

TP36

VLDO_S

 Test point

TP10

REFCAP_P

Test point

TP37

REFCAP_S

 Test point

TP47

RESET

Test point

External RESET will apply to both the primary and secondary device.