SNAU288 December   2023 LMX1906-SP

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Evaluation Setup Requirement
      2. 2.1.2 Connection Diagram
        1. 2.1.2.1 How to Enable Full SPI Control
      3. 2.1.3 Power Requirements
      4. 2.1.4 Pin Mode Strapping
      5. 2.1.5 Reference Clock
        1. 2.1.5.1 Output Connections
        2. 2.1.5.2 Header Information
        3. 2.1.5.3 Default Configuration
        4. 2.1.5.4 How to Generate SYSREF
        5. 2.1.5.5 Multiplier Mode Example
        6. 2.1.5.6 Divider Mode Example
        7. 2.1.5.7 Hybrid Mode: SPI and Pin Mode
  8. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
    3. 3.3 USB2ANY Interface
  9. 4Implementation Results
    1. 4.1 Buffer, Divider, and Multiplier Modes
    2. 4.2 SYSREF Generation
    3. 4.3 SYSREF Delay Generators
  10. 5Hardware Design Files
    1. 5.1 Schematic
    2. 5.2 PCB Layout
      1. 5.2.1 PCB Layer Stack-Up
    3. 5.3 Bill of Materials
  11. 6Additional Information
    1. 6.1 Troubleshooting Guide
      1. 6.1.1 General Guidance
      2. 6.1.2 If Output Is Not Seen on CLKOUT
      3. 6.1.3 If Device Features Are Not Active
      4. 6.1.4 If Multiplier Frequency Is Not Accurate
      5. 6.1.5 If Divider Frequency Is Not Accurate
      6. 6.1.6 If SYSREF Is Not Observed
    2. 6.2 Trademarks

2.1.1 Evaluation Setup Requirement

At a minimum, evaluation of the buffer mode requires:

  • A DC power supply capable of at least 3.1 V, 2 A
  • A high-quality signal source, such as an SMA100B
  • A spectrum analyzer or signal analyzer
  • A PC with a USB port, running Windows 7 or a more recent version of Windows
  • Texas Instruments Clocks and Synthesizers TICS Pro software
Full evaluation requires the following additional hardware:

  • A high-speed 4-CH oscilloscope capable of resolving 5-ps step size for SYSREF delay tuning
  • A 2-CH arbitrary function generator or other pulse source capable of outputting complementary LVDS pulses and DC levels (1.25 V ± 0.2 V, differential, into 100-Ω DC load) for triggering SYSREF, SYNCing the dividers, and determining SYSREF windowing values
  • A phase noise analysis system capable of measuring at up to 18 GHz