SNLA132G October   2011  – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview of Internal Test Pattern Generation
    1. 2.1 Color Mode
    2. 2.2 Video Timing Modes
    3. 2.3 Clock Generation
    4. 2.4 Pattern Selection
    5. 2.5 Pattern Inversion
    6. 2.6 Auto-Scrolling
  4. 3Serial Control Bus Registers for Internal Test Pattern Generation
    1. 3.1 Direct Register Map
      1. 3.1.1 Control and Configuration
      2. 3.1.2 Indirect Access Address and Data
      3. 3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source
    2. 3.2 Indirect Register Map
      1. 3.2.1 General Control
      2. 3.2.2 Internal Timing Control
      3. 3.2.3 Auto-Scrolling Control
  5. 4Configuration Examples
    1. 4.1 Auto-Scrolling Configuration
    2. 4.2 Internal Default Timing Configuration
    3. 4.3 Custom Display Configuration
    4. 4.4 1080p60 with External Clock Example Configuration
    5. 4.5 Resolution Readback Example
  6. 5Conclusion
  7. 6References
  8. 7Revision History

2.3 Clock Generation

The FPD Link devices listed in Table 1-1 include an internal oscillator which can be used as a reference to generate video with internal timing. Table 2-1 describes the nominal oscillator frequencies for each device. The examples in this document assume the default 200MHz nominal oscillator frequency is used unless otherwise noted.

Table 2-1 Internal Oscillator Frequencies
DeviceNominal Internal Oscillator Frequency
DS90UH925Q-Q1/DS90UB925Q-Q1200 MHz
DS90UB921-Q1200 MHz
DS90UH927Q-Q1/DS90UH927Q-Q1200 MHz
DS90UH947-Q1/DS90UH947-Q1200 MHz or 800 MHz by selection
DS90UH929-Q1/DS90UB929-Q1200 MHz or 800 MHz by selection
DS90UH949-Q1/DS90UB949-Q1200 MHz or 800 MHz by selection
DS90UH949A-Q1/DS90UB949A-Q1200 MHz or 800 MHz by selection
DS90UH941AS-Q1/DS90UB941AS-Q1200 MHz or 800 MHz by selection
DS90UH926Q-Q1/DS90UB926Q-Q1200 MHz
DS90UB924-Q1160 MHz
DS90UH928Q-Q1/DS90UB928Q-Q1160 MHz
DS90UH948-Q1/DS90UB948-Q1140 MHz
DS90UH940-Q1/DS90UB940-Q1140 MHz
DS90UH940N-Q1/DS90UB940N-Q1140 MHz

The pattern generator can be configured to use an internal oscillator source to generate the pixel clock and timing signals necessary to drive a wide variety of display configurations using an M/N divider. For all devices besides the DS90Ux941AS-Q1, DS90Ux949-Q1, DS90Ux949A-Q1, DS90Ux929-Q1, and DS90Ux947-Q1, the M value is assumed to be 1 and the valid range of values for N is 2 to 63. For DS90Ux941AS-Q1, DS90Ux949-Q1, DS90Ux949A-Q1, DS90Ux929-Q1, and DS90Ux947-Q1, the M and N values can both be varied as an 800-MHz oscillator option is available. The internal reference oscillator is multiplied by the M/N ratio to generate the target pixel clock (PCLK = M/N*(Oscillator Frequency)). Table 2-2 shows example video modes, divider values, and refresh rates.

Table 2-2 Sample Video Modes and Refresh Rates (200MHz Oscillator)
Active ResolutionTotal ResolutionTotal PixelsDivider Ratio (4)Minimum Refresh (Hz)Typical Refresh (Hz)(1)Maximum Refresh (Hz)
HorizontalVerticalHorizontalVertical
4002404802881382402448.260.372.3
96016011521922211841548.260.372.3
640480800525420000847.659.571.4
800480840485407400849.161.473.6
12804801320485640200550.062.575.0
8006001056628663168548.360.372.4
102476813448061083264349.261.573.9
128076814407981149120346.458.069.6
128080014508441223800343.654.565.4
136076817927951424640337.446.856.2
1920(2)1080(2)204711252302875323.228.934.7
1920(3)1080(3)220011252302875230.443.456.5
(1) The minimum, typical, and maximum refresh rates are related to the device internal oscillator reference frequency variation of 140 MHz (min), 200 MHz (typ), and 260 (max) MHz respectively.
(2) 1080p30 target resolution
(3) 1080p60 target resolution - only supported on 94x dual link devices
(4) The divider ratios in this table assume the M value for the M/N divider is 1
Note:

The DS90Ux928Q-Q1 and DS90UB924-Q1 deserializers require extra configuration to use the internally generated pixel clock. Refer to Table 3-3 for additional details.