SNLA426 june   2023 DS320PR1601 , DS320PR410

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. Introduction
  5. PCIe Gen3, Gen4, and Gen5 Loss Budget
  6. Minimum Eye Width
  7. Cross Talk Mitigation
  8. Humidity and Temperature Insertion Loss
  9. Critical Signals
  10. General High-Speed Signal Routing
  11. PCB Grain and Fiber Weave Selection
  12. PCB Material Loss Budget
  13. 10High-Speed Signal Trace Impedance
  14. 11High-Speed Signal Trace Length Matching
  15. 12Differential Trace Routing Guidelines
  16. 13Differential-Inter-Pair Matching
  17. 14Intra-pair Length Matching
  18. 15Trace Bends
  19. 16Minimum Differential Trace-To-Trace Distance
  20. 17Serpentine Guidelines
  21. 18High-Speed Differential Signal Quick Rules
  22. 19High-Speed Differential Pair Reference Plane
  23. 20Via Staggering
  24. 21Via Stubs
  25. 22Via Pads
  26. 23Via Discontinuity Mitigation
  27. 24Back-Drill Stubs
  28. 25AC Coupling Capacitors Placement
  29. 26AC Coupling Capacitor Physical Placement
  30. 27Auxiliary Signal AC Match Termination
  31. 28Suggested PCB Stack-ups
  32. 29Summary
  33. 30References

Suggested PCB Stack-ups

TI recommends a PCB of at least six layers. Table 28-1 provides example PCB stack-ups.

Table 28-1 PCB Stack-up Examples
DS320PR1601EVM Alternate 8-LAYER Alternate 10-LAYER
High speed signal Signal Signal
Ground Ground Ground
Low speed signal Signal Signal
Power Power Power/Ground
Power Power Signal
Low speed signal Signal Signal
Ground Ground Power/Ground
High speed signal Signal Signal
Ground
Signal

Notes:

  1. Route directly adjacent signal layers at a 90° offset to each other

The plane can be split depending on specific board considerations. Make sure that traces on adjacent planes do not cross splits.