SNLA431 January   2024 DP83TC812R-Q1 , DP83TC812S-Q1

 

  1.   1
  2.   Trademarks
  3. 1Preface
  4.   Notational Conventions
  5. 2Related Documentation
  6. 3Support Resources
  7. 4Troubleshooting the PHY Application
    1. 4.1  Schematic and Layout Checklist
    2. 4.2  Verify Successful Power-up of PHY
    3. 4.3  Peripheral Pin Checks
      1. 4.3.1 Probe the RESET_N pin
      2. 4.3.2 Probe the INH pin
      3. 4.3.3 Probe the CLKOUT pin
      4. 4.3.4 Probe the Serial Management Interface (MDC, MDIO) Pins
    4. 4.4  Register Dump Comparison
    5. 4.5  Verifying Strap Configurations
    6. 4.6  Check the MDI Signal
    7. 4.7  Link Up Failed Common Issues
    8. 4.8  Signal Quality Check
    9. 4.9  Power Up Timing
    10. 4.10 Loopback Testing
    11. 4.11 Debugging the MAC Interface
    12. 4.12 Verify Open Alliance PMA Compliance
    13. 4.13 Tools and References
      1. 4.13.1 DP83TC812 Register Access
      2. 4.13.2 DP83TC812 USB2MDIO Scripts
      3. 4.13.3 Extended Register Access
      4. 4.13.4 Software and Driver Debug on Linux
        1. 4.13.4.1 Commonly Seen Linux Terminal Outputs
  8. 5Conclusion

4.4 Register Dump Comparison

Read each of the below registers and verify the values shown. Note that the initial values of some registers can vary based on strap options. Comparing a register dump to the one shown helps to highlight any values different from the expected.

The below register dump shows the expected values when link is up and the PHY is in RGMII mode, MDI slave, with PHY address 0xA.

Table 4-4 DP83TC812 Register Value Check
REGISTER ADDRESS

REGISTER NAME

REGISTER VALUE

DESCRIPTIONS

0x0000

BMCR

0x2100

0x0001

BMSR

0x0065

Bit[2] shows that link is up

0x0002

PHYIDR1

0x2000
0x0003

PHYIDR2

0xA271

0xA271 is the unique identifier for the DP83TC812 PHY. A value other than this indicates a different PHY is connected.

0x0010

PHYSTS

0x0005

0x0011

PHYSCR

0x010B
0x0012

MISR1

0xE400

Indicates the presence of any interrupts

0x0013

MISR2

0x0000

Indicates the presence of any interrupts
0x0015

RECR

0x0000

Receive error counter

0x0016

BISCR

0x0100
0x0018

MISR3

0x5825

Indicates the presence of any interrupts
0x0019

REG_19

0x0C0A

Bits 4-0 is the decoded PHY address from strap

0x001B

TC10_ABORT_REG

0x0000
0x001E

CDCR

0x0000

0x018B(1)

LPS_CFG20x1C0BBit[6] indicates autonomous or managed mode. Note the PHY will not automatically link up if this bit is 0.

0x045D(1)

CHIP_SOR_1

0x408C

Sampled PHY Strap configurations after power up or reset. Verify with strap tool in the schematic checklist for specific configurations.

0x0600(1)

RGMII_CTRL

0x0038

Bit[3] indicates that RGMII mode is enabled

0x0608(1)

SGMII_CTRL_1

0x007B

Bit[9] indicates that SGMII mode is disabled

0x0648(1)

RMII_CTRL_1

0x0120

Bit[6] indicates that RMII mode is disabled

0x1834(1)

MMD1_PMA_CTRL_2

0x8000

PHY Master/Slave configuration. Value will read 0xC000 in master mode and 0x8000 in slave mode

Note:

Registers above 0x1F are extended registers and must be accessed using the extended register access procedure.