SNLA437 December   2023 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83825I , DP83826E , DP83826I

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83822 Application Overview
  5. 2Troubleshooting the PHY Application
    1. 2.1  Schematic and Layout Checklist
    2. 2.2  Verify Successful Power-up of PHY
    3. 2.3  Read and Check Register Values
    4. 2.4  Peripheral Pin Checks
      1. 2.4.1 Probe the RESET_N Signal
      2. 2.4.2 Probe the RBIAS pin
      3. 2.4.3 Probe the Serial Management Interface (MDC, MDIO) Signals
      4. 2.4.4 Probe the MDI Signals
    5. 2.5  Verifying Strap Configurations During Initialization
    6. 2.6  Debugging Link Quality
    7. 2.7  Built-In Self Test With Various Loopback Modes
    8. 2.8  Debug the Fiber Connection
    9. 2.9  Debug the MAC Interface
    10. 2.10 Debug the Start of Frame Detect
    11. 2.11 Tools and References
      1. 2.11.1 DP83822 Register Access
      2. 2.11.2 Extended Register Access
      3. 2.11.3 Software and Driver Debug on Linux
        1. 2.11.3.1 Common Terminal Outputs and Solutions
  6. 3References

2.9 Debug the MAC Interface

RGMII

The RGMII signals are summarized in Table 2-10.

Table 2-10 RGMII Signals
Function Pins
Data Signals TX_D[3:0]
RX_D[3:0]

Transmit and Receive Signals

 TX_CTRL
RX_CTRL
Clock TX_CLK
RX_CLK
GUID-84C04287-331D-461A-A63B-EF82C34B566A-low.gif Figure 2-12 RGMII Signaling

In order for the MAC to be able to transmit and receive the correct data from the PHY, the correct RGMII modes must be selected such that both the PHY and the MAC are not simultaneously in align mode or shift mode for the Tx and Rx side. Table 2-11 lists the correct RGMII delay configurations.

Table 2-11 RGMII Shift Configurations
MAC Configuration Required PHY Configuration
RGMII Align on Rx RGMII Shift on Rx
RGMII Shift on Rx RGMII Align on Rx
RGMII Align on Tx RGMII Shift on Tx
RGMII Shift on Tx RGMII Align on Tx

Reference the waveforms below to verify the expected MAC data and clock signals for RGMII Mode. The table displays specs taken from the device-specific data sheet that are shown in the waveforms.

GUID-20231103-SS0I-2QX4-TJZW-HQXGZDM6XHNR-low.svg Figure 2-13 RX_CLK and RX_D0 Timing in RGMII Align Mode (Yellow Waveform (Channel 1) = RX_CLK, Blue Waveform (Channel 2) = RX_D0)
GUID-20231103-SS0I-GGMR-GGSD-PQ8CG7399W93-low.svg Figure 2-14 RX_CLK and RX_D0 Timing in RGMII RX Shift Mode (Yellow Waveform (Channel 1) = RX_CLK, Blue Waveform (Channel 2) = RX_D0)

For RGMII Rx shift mode, verify that RX_CLK is shifted by 3.5 ns and for RGMII TX Clock Shift that TX_CLK is shifted by 3.5 ns.

Table 2-12 RGMII Input Timing Specifications
Parameter Test Condition Min Typ Max Unit
Tcyc TX_CLK / Clock Cycle Duration 36 40 44 ns
Tsetup(align) TX_D[3:0], TX_CTRL setup to TX_CLK (align mode) 1 2 ns
Thold(align) TX_D[3:0], TX_CTRL hold to TX_CLK (align mode) 1 2 ns
Table 2-13 RGMII Output Timing Specifications
Parameter Test Condition Min Typ Max Unit
Tskew(align)

RX_D[3:0], RX_CTRL delay from RX_CLK (align mode)

-500

0

 ps
Tsetup(shift) RX_D[3:0], RX_CTRL delay from RX_CLK (shift mode enabled, default) 1.2 2 ns
Tcyc RX_CLK / Clock Cycle Duration 36 40 44 ns
Duty_G RX_CLK / Duty Cycle 40 50 60 %
Tr/Tf RX_CLK / Rise, Fall Time (20% to 80% ) 750 ps

RMII

The incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification from the RMII consortium. The purpose of this interface is to provide a reduced pin count alternative to the IEEE 802.3u MII as specified in Clause 22. Architecturally, the RMII specification provides an additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII. The offers two types of RMII operations: RMII Slave and RMII Master. In RMII Slave operation, the operates off of a 50-MHz CMOS-level oscillator connected to the XI pin and shares the same clock as the MAC. In RMII Master operation, the operates off of either a 25-MHz CMOS-level oscillator connected to XI pin or a 25-MHz crystal connected across XI and XO pins. A 50-MHz output clock referenced from any of the three GPIOs is connected to the MAC.

Note: If RMII Master mode is configured through bootstraps, a 50-MHz output clock will automatically be enabled on RX_D3 (GPIO3).

The RMII specification has the following characteristics:

  • Supports 100BASE-FX, 100BASE-TX and 10BASE-Te.
  • Single clock reference sourced from the MAC to PHY (or from an external source)
  • Provides independent 2-bit wide transmit and receive data paths
  • Uses CMOS signal levels, the same levels as the MII interface

In this mode, data transfers are two bits for every clock cycle using the internal 50-MHz reference clock for both transmit and receive paths.

The RMII signals are summarized in Table 2-14.

Table 2-14 RMII Signals
Function Pins
Data Signals TX_D[1:0]
RX_D[1:0]
Transmit and Receive Signals TX_EN
CRS_DV
GUID-79F70463-8CB9-4640-914C-C3A2B2628A5E-low.gif Figure 2-15 RMII Slave Signaling
GUID-E7F22B5E-DCFB-4376-8569-A73208DEDCA9-low.gif Figure 2-16 RMII Master Signaling
Note: For using the DP83822 in RMII repeater mode, see the DP83822 RMII Repeater Mode.

For more information on reduced media independent interface, see the Reduced Media Independent Interface (RMII) section of the DP83822 Robust, Low Power 10/100 Mbps Ethernet Physical Layer Transceiver Data Sheet.

GUID-20231103-SS0I-ZHLH-LNDR-QSGWJNHWTR5L-low.svg Figure 2-17 RX_CLK and RX_D0 Timing for RMII (Yellow Waveform (Channel 1) = RX_CLK, Blue Waveform (Channel 2) = RX_D0)

MII

The Media Independent Interface is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC . The MII is fully compliant with IEEE 802.3-2002 clause 22.

The MII signals are summarized in Table 2-15.

Table 2-15 MII Signals
Function Pins
Data Signals TX_D[3:0]
RX_D[3:0]
Transmit and Receive Signals TX_EN
RX_DV
Line-Status Signals CRS
COL
Clock TX_CLK
RX_CLK
GUID-916845DC-3BF2-4C23-A17F-172157055696-low.gif Figure 2-18 MII Signaling

Additionally, the MII interface includes the carrier sense signal (CRS), as well as a collision detect signal (COL). The CRS signal asserts to indicate the reception or transmission of data. The COL signal asserts as an indication of a collision which can occur during Half-Duplex mode when both transmit and receive operations occur simultaneously.

GUID-20231103-SS0I-CJXQ-DPHN-CXH7ZMSNCKLD-low.svg Figure 2-19 RX_CLK and RX_D0 Timing for MII (Blue Wave (Channel 2) = RX_CLK, Purple Wave (Channel 3) = RX_D0)