SNLA448 November   2023 LMK3H0102

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Test Setup
  6. 3Test Procedure
  7. 4Explanation of TI's PCIe Compliance Tool
  8. 5LMK3H0102 Test Results
    1. 5.1 LMK3H0102 Test Results Summary
    2. 5.2 PCIe Tool Input File Waveforms for the LMK3H0102 Family
    3. 5.3 LMK3H0102 Detailed Jitter Measurements
  9. 6Summary
  10. 7References

Test Setup

TI’s PCIe Compliance Reports display the analysis of a device’s phase noise or jitter in regards to meeting PCIe requirements. The LMK3H0102 family is characterized at max operating temperature of 85°C and a lowest supply voltage of 1.71 V. This PCIe compliance report displays test results under typical conditions. For the LMK3H0102 family the operating temperature is at 25°C and the supply voltage is at 3.3 V.

The hardware setup consists of a device under test, power supply, attenuators, limiter, balun (for frequency domain only), thermal force unit, test load board, and phase noise analyzer (PNA, for frequency domain) or oscilloscope (for time domain). The device is reference-less, and does not require signal from a signal generator. The internal BAW resonator is the clock source for the device.

For the frequency domain measurements, the differential outputs of the device are connected to a balun to convert them to a single-ended signal and then route that signal to a PNA, as shown on Figure 2-1.

GUID-20231110-SS0I-H4XV-J1NC-PP3JJ4KLJ7PP-low.svg Figure 2-1 TI's PCIe Compliance Test Hardware Setup for Frequency Domain Measurements

For time domain measurements, the differential outputs (both positive and negative pins) of the device are routed directly to an oscilloscope, as shown on Figure 2-2. Also, when obtaining data for the time domain measurements, the PCIe test load is a 15 dB loss trace at 4 GHz.

GUID-20231110-SS0I-QHR4-KSVC-ZJRBGMMGSLMF-low.svg Figure 2-2 TI's PCIe Compliance Test Hardware Setup for Time Domain Measurements