SNLS299I
May 2008 – June 2020
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Functional Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Descriptions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Performance Curves
7
Parameter Measurement Information
8
Detailed Description
8.1
Functional Block Diagram
8.2
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Detailed Design Procedure
9.2.1.1
Power Decoupling Recommendations
9.2.1.2
Termination
9.2.1.3
Input Failsafe Biasing
9.2.1.4
Probing LVDS Transmission Lines
9.2.1.5
Cables and Connectors, General Comments
10
Layout
10.1
Layout Guidelines
10.1.1
Differential Traces
10.1.2
PC Board Considerations
11
Device and Documentation Support
11.1
Device Support
11.2
Community Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
5
Pin Configuration and Functions
D Package
SOIC 8 Pin
Top View
Pin Descriptions
Pin Number
Name
Description
1
R
IN
1-
Inverting receiver input pin
4
R
IN
2-
2
R
IN
1+
Non-inverting receiver input pin
3
R
IN
2+
6
R
OUT
2
Receiver output pin
7
R
OUT
1
8
V
CC
Power supply pin, +3.3V +/- 0.3V
5
GND
Ground pin