SNVA103B October 2005 – February 2022 LM2743
When using a DC power supply to set a reference voltage (VREF), connect a capacitor (C20) from VDCS to GND to filter the DC power supply. A good starting point is 10 µF, but it may need to be varied depending on the magnitude of the DC power supply noise (any make of capacitor will do as long as the capacitance is maintained within the operating temperature range). Remove R10 and place a 0-Ω jumper in designator R12.
Designators R12 and R13 are provided for DDR SDRAM (double data rate synchronous dynamic random access memory) active termination design. Set VREF to half the DDR supply voltage by using designators R12 and R13 as a voltage divider. Remove resistors R7 and R10 and capacitor C21, and connect the DDR supply voltage rail to terminal VDCS. Refer to Figure 4-2. The modified circuit in Figure 4-1 can sink or source current in excess of 3 A. A load transient response applied to the output of Figure 4-2 is provided in Figure 5-1.
Do not exceed 5.6 V on the VCC pin of the demo board. The board layout connects both the input voltage of the LM4140-1.0 (pin 2) and the control section of the LM2744 (VCC). The maximum DC supply voltage for the control section of the LM2744 is 6 V, while 5.6 V is the maximum rating for any input pin of the LM4140. If the design requires the control section of the LM2744 to be 6 V, a shunt zener reference can be placed at designator location (D3) to maintain the input voltage of the LM4140 between 1.8 V and 5.5 V. The cathode of the zener is connected to the input of the LM4140 and the anode to GND. The resistance of R10 must be selected to supply the appropriate amount of biasing current into the zener and the LM4140 (refer to the Electrical Characteristics table of the LM2744 Low Voltage N-Chan MOSFET Synch Buck Regr Cntrl w/ Ext Ref data sheet.