SNVA881 November   2019 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1 , LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1

 

  1.   Stability Considerations for LP8756x-Q1 and LP8752x-Q1
    1.     Trademarks
    2. 1 Introduction
    3. 2 Stability Target
    4. 3 Use Cases
    5. 4 Measurements
      1. 4.1 Measurement Setup
      2. 4.2 Measurement Results
    6. 5 Simulations
      1. 5.1 Simulation Model
      2. 5.2 Simulation Results
    7. 6 Summary
    8. 7 References

Stability Target

The loop is stable when the system's feedback is negative and limits the gain. In other words, the loop is unstable if the negative feedback turns into positive feedback, which consequently saturates the output to supply limits. Negative feedback will turn in to positive feedback if the phase changes by 180 degrees and the closed loop gain is positive. The frequency is the point of interest in the measurements where the phase crosses 0 or ±180 degrees and the gain falls below 0 dB (the gain and phase margin is measured from those frequencies). The gain margin defines how much more gain the loop may have until it becomes unstable, and the phase margin defines how much phase shift there may be until the loop becomes unstable.

Generally the loop has sufficient stability margin if it has over 45 degrees of phase margin and over 10 dB of gain margin (these are often the design targets). Even the lower margins and theoretically the loop are stable, if both the gain and phase margins are larger than 0 dB or 0 degrees, but 10 dB gain margin and 45 degree phase margin are considered a standard safety buffer for stability. Higher stability margins are possible at the expense of slower transient response. For the LP8756x-Q1 and LP8752x-Q1 devices, the phase margin of 45 degrees and 10 dB gain margin are a good compromise between stability and transient response. Many different parameters affect both the phase and gain margin, and this application report focuses on systematically iterating through some of the most significant parameters. Layout has an impact on phase margin as well, but iterating through multiple different layouts was not possible. To maximize the phase margin, the PCB parasitic inductance should be minimized and the point of load capacitors should be placed as close to the load as possible. For more information about phase margin and closed loop stability, refer to Switch-mode power converter compensation made easy article.

Please note that the inductor value should be kept at a constant 470 nH, as the internal compensation of the device is configured for previously mentioned inductance. The device verification and validation has been done using 470 nH inductors.