SNVAA94 November   2023 LM5113-Q1 , LMG1205 , LMG1210

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Bootstrap Overcharge
  6. 3 Modeling Bootstrap Overcharge
  7. 4 Changing Bootstrap Components
  8. 5 Zener Diode Method
  9. 6 Schottky Diode Method
  10. 7 Overvoltage Clamp Method
  11. 8 Active Switch Method
  12. 9 Synchronous GaN Bootstrap Method
  13. 10Other Methods of Preventing Bootstrap Overcharge
    1. 10.1 Reducing Dead Time
    2. 10.2 Opting for a Bias Supply
    3. 10.3 Adjusting for Gate Voltage
  14. 11Summary
  15. 12References

3 Modeling Bootstrap Overcharge

One way to model bootstrap overcharge is using charge (Q). The bootstrap current charges Cboot during the charging period. Then, Cboot discharges when sourcing current to drive the high-side FET. Cboot reaches steady-state voltage when the balance of charging and discharging is equal. In Figure 3-1, the top graph shows the voltage rise and fall over the charging and discharging period. The bottom graph shows the Qin and Qout based on current.

GUID-20231012-SS0I-Z1CR-8DKN-L51PWHBQCMVB-low.svg Figure 3-1 Plot From a Simulation of Bootstrap Overcharge

Figure 3-1 shows a simulation of a half-bridge where Cboot overcharges by nearly 2 V. During the dead time, a bootstrap current (Iboot) flows through Cboot due to the increased voltage potential caused by negative HS. During the normal charging period where HS is 0 V, Cboot does not charge because the voltage across Cboot is already higher than VDD. Cboot charges again during the next dead time, but slightly less as the load (IL) and HS decrease. Finally, Cboot discharges into the gate charge (Qg) of the high-side FET and the reverse recovery (Qrr) of the bootstrap diode.

The integral of Iboot gives the bootstrap charge (Qin) over time. The bootstrap discharge (Qout) can be calculated or measured. When Qin and Qout are equal, Cboot reaches steady-state voltage. As shown in Figure 3-1, the area of Qin 1 and Qin 2 equals the area of Qrr and Qg.

Equation 2 and Equation 3 describe this behavior:

Equation 2. Q i n = ∫ t t + D T 1 I b o o t ( t )   d t +   ∫ t t + D T 2 I b o o t ( t )   d t
Equation 3. I b o o t ( t ) = V D D - V F ( t ) - V b o o t ( t ) + V S D ( t ) R b o o t

Qout primarily consists of Qg to drive the high-side switch, leakage from the driver circuits, gate-source leakage of the GaN FET, and reverse recovery in the bootstrap diode. In most cases, Qg alone is sufficient to estimate Qout because Qg is the most significant factor. FET data sheets often include a Qg versus Vgs plot, which offers a way to estimate the steady-state voltage.

Equation 2 and Equation 3 guide understanding into the available options for addressing bootstrap overcharge. Relevant information is sometimes available late in the design process, making calculating parameters like Vf (which changes with Iboot) difficult. Additionally, the results change over load and temperature. Simulation offers a more straightforward, accurate method than calculating for determining bootstrap overcharge.