SNVU828 March   2022 LP87562-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Sequencing
  4. 3Register Bits Loaded From OTP Memory

1 Introduction

This technical reference manual can be used as a reference for the LP87562S-Q1 default register bits after power up. This technical reference manual does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the LP8756x-Q1 Four-Phase 16-A Buck Converter With Integrated Switches data sheet.

Table 1-1 provides the quick overview of each regulator default OTP settings. Sequencing provides an overview of default power up and power down sequence. Table 3-1 lists all the default OTP settings after power up.

Table 1-1 Main OTP Settings for regulators
DescriptionBit Name Value
Device identification OTP configuration OTP_ID D2h
BUCK0...2 (3-phase operation)Output voltageBUCK0_VSET800 mV
Enable (ENx pin or I2C register write)EN_BUCK0, EN_PIN_CTRL0, BUCK0_EN_PIN_SELECT EN1 pin
Startup delayBUCK0_STARTUP_DELAY0 ms
Shutdown delayBUCK0_SHUTDOWN_DELAY0 ms
Force PWM BUCK0_FPWM Forced PWM
Force multiphase BUCK0_FPWM _MP Forced multi-phase operation
Peak current limitILIM0, ILIM1, ILIM35.0 A
Maximum load currentN/A12 A
Slew rateSLEW_RATE03.8 mV/us
BUCK3 Output voltage BUCK3_VSET 1800 mV
Enable (ENx pin or I2C register write) EN_BUCK3, EN_PIN_CTRL3, BUCK3_EN_PIN_SELECT EN2 pin
Startup delay BUCK3_STARTUP_DELAY 0 ms
Shutdown delay BUCK3_SHUTDOWN_DELAY 0 ms
Force PWM BUCK3_FPWM Forced PWM
Peak current limit ILIM3 5.0 A
Maximum load current N/A 4 A
Slew rate SLEW_RATE3 3.8 mV/us
Spread spectrum EN_SPREAD_SPEC Enabled
Switching frequency N/A 2 MHz
I2C addressN/A60h