SPMA057D January   2018  – June 2022 TM4C1290NCPDT , TM4C1290NCPDT , TM4C1290NCZAD , TM4C1290NCZAD , TM4C1292NCPDT , TM4C1292NCPDT , TM4C1292NCZAD , TM4C1292NCZAD , TM4C1294KCPDT , TM4C1294KCPDT , TM4C1294NCPDT , TM4C1294NCPDT , TM4C1294NCZAD , TM4C1294NCZAD , TM4C1297NCZAD , TM4C1297NCZAD , TM4C1299KCZAD , TM4C1299KCZAD , TM4C1299NCZAD , TM4C1299NCZAD , TM4C129CNCPDT , TM4C129CNCPDT , TM4C129CNCZAD , TM4C129CNCZAD , TM4C129DNCPDT , TM4C129DNCPDT , TM4C129DNCZAD , TM4C129DNCZAD , TM4C129EKCPDT , TM4C129EKCPDT , TM4C129ENCPDT , TM4C129ENCPDT , TM4C129ENCZAD , TM4C129ENCZAD , TM4C129LNCZAD , TM4C129LNCZAD , TM4C129XKCZAD , TM4C129XKCZAD , TM4C129XNCZAD , TM4C129XNCZAD , TMP1826 , TMP1826 , TMP1827 , TMP1827

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction to 1-Wire
    1. 1.1 Bus Requirements
    2. 1.2 Powering
  4. 2Functional Description
    1. 2.1 Signaling on 1-Wire
    2. 2.2 Address Format of the 1-Wire Device
    3. 2.3 Typical Communication Flow on the 1-Wire Bus
  5. 3Functions Available in TivaWare for C Series for 1-Wire Module
  6. 4Enumeration
    1. 4.1 Legacy Search Algorithm
      1. 4.1.1 Steps of the 3-Bit Search Algorithm
    2. 4.2 Fast Search Algorithm
  7. 5Summary
  8. 6References
  9. 7Revision History

Introduction to 1-Wire

1-Wire is a communication bus designed to interface temperature sensors and non-volatile memory devices like TMP1826 with a single wire that supports both communication and power delivery. This system is used for low-speed and low-power communication devices. There are two speed modes available: standard speed and overdrive speed. The achievable data rate with standard speed is typically 8.33 kbit/s, while overdrive mode speed communication can perform up to 90 kbits/s.

This protocol uses a single data line for data transmission from one device to another device. The bus is half duplex so that data can move in both directions, but not at the same time. When required, an extra wire can also be used to power up the devices.

The protocol supports one (single drop) or multiple target devices (multi drop) on the bus. There is also a single controller on the bus that controls the transfer of information on the bus. The controller initiates all transfers on the data line. Transfer of data is only possible between controller and target devices, so data cannot be transferred between devices.

A clock is not required for this protocol as each target device is clocked by an internal oscillator synchronized to the falling edge of the bus. When transferring a byte, the least significant bit is transferred first.

Figure 1-1 Bus Topology