SPNA233B May   2016  – February 2020 RM41L232 , RM41L232 , RM42L432 , RM42L432 , RM44L520 , RM44L520 , RM44L920 , RM44L920 , RM46L430 , RM46L430 , RM46L440 , RM46L440 , RM46L450 , RM46L450 , RM46L830 , RM46L830 , RM46L840 , RM46L840 , RM46L850 , RM46L850 , RM46L852 , RM46L852 , RM48L530 , RM48L530 , RM48L540 , RM48L540 , RM48L730 , RM48L730 , RM48L740 , RM48L740 , RM48L940 , RM48L940 , RM48L950 , RM48L950 , RM48L952 , RM48L952 , RM57L843 , RM57L843 , TMS570LC4357 , TMS570LC4357 , TMS570LC4357-EP , TMS570LC4357-EP , TMS570LC4357-SEP , TMS570LC4357-SEP , TMS570LS0232 , TMS570LS0232 , TMS570LS0332 , TMS570LS0332 , TMS570LS0432 , TMS570LS0432 , TMS570LS0714 , TMS570LS0714 , TMS570LS0714-S , TMS570LS0714-S , TMS570LS0914 , TMS570LS0914 , TMS570LS1114 , TMS570LS1114 , TMS570LS1115 , TMS570LS1115 , TMS570LS1224 , TMS570LS1224 , TMS570LS1225 , TMS570LS1225 , TMS570LS1227 , TMS570LS1227 , TMS570LS2124 , TMS570LS2124 , TMS570LS2125 , TMS570LS2125 , TMS570LS2134 , TMS570LS2134 , TMS570LS2135 , TMS570LS2135 , TMS570LS3134 , TMS570LS3134 , TMS570LS3135 , TMS570LS3135 , TMS570LS3137 , TMS570LS3137

 

  1.   Hercules PLL Advisory SSWF021#45 Workaround
    1.     Trademarks
    2. 1 Background
    3. 2 Implementation
      1. 2.1 Which Function to Use
        1. 2.1.1 _errata_SSWF021_45_pll1()
        2. 2.1.2 _errata_SSWF021_45_pll2()
        3. 2.1.3 _errata_SSWF021_45_both_plls()
      2. 2.2 Where to Place the Function Call
      3. 2.3 Parameters and Return Value
        1. 2.3.1 Input Parameter
        2. 2.3.2 Return Value
      4. 2.4 Execution Time
    4. 3 Detailed Description
  2.   Revision History

2 Implementation

The header file “errata_SSWF021_45.h” contains the function prototypes and should be included in the user’s source file that calls the workaround function. The header file “errata_SSWF021_45_defs.h” defines values used in the “errata_SSWF021.c” file. It makes the source file independent of HALCoGen.

NOTE

The workaround functions do not set the PLL to the customer's desired frequency, nor do they leave the PLL enabled. These steps should be performed after successful completion of the workaround routine. The PLL settings in the workaround routine were chosen to minimize the lock time and to be valid over the range of 5 MHz to 20 MHz crystal frequency. Changing these settings may affect the proper execution of the workaround routine.