SPRACT9 September   2020  – MONTH  AM6526 , AM6528 , AM6546 , AM6548 , AM68 , AM68A , AM69 , AM69A , DRA829J , DRA829V , TDA4VM , TDA4VM-Q1

 

  1.   Trademarks
  2. 1Tuning Algorithm Overview
  3. 2Hardware Tuning Algorithm
  4. 3SW Tuning Algorithm

2 Hardware Tuning Algorithm

Hardware tuning is executed by setting MMCSDx_HOST_CONTROL2[6] EXECUTE_TUNING bit to ‘1’ and issuing CMD19/CMD21 repeatedly. The hardware then automatically sequences through all 32 delay ratios and selects the optimal one for functionality runs.

When the hadware tuning mechanism is used, you do not have visibility into the pass and fail result of each delay ratio elements, nor the final delay ratio element chosen to be utilized during functionality runs. This means a lack of visibility into the inner working of the hardware tuning module for debug needs. As a result, the software tuning algorithm is the recommended method of implementation on all systems.