SPRACU5C June 2021 – September 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
When the boot mode configuration to the buffer is being driven from external inputs, the boot mode configuration inputs are recommended to be stable during the processor cold reset.
When using Ethernet Boot (CPSW3G, Take note of i2331 CPSW: Device lockup when reading CPSW register recommendations) and RGMII interface, select a EPHY with capability to enable RGMII_ID mode on the EPHY RX data path and disables RGMII_ID mode on the TX data path by default (the processor implements RGMII_ID on the TX channel). The processor ROM is EPHY agnostic and will not programmatically enable/disable RGMII_ID mode on attached EPHYs. This is accomplished via pin strapping on the EPHY.