In variable frequency applications, like LLC, the control ISR, where the period and compare registers will be updated, runs at a fixed frequency, which is asynchronous to the PWM switching frequency. Thus, it may happen that the ISR is triggered at a point in time close to the end of the switching cycle. If this is the case, it is possible that some part of the ISR code that updates the ePWM registers executes before the end of the cycle, while the remainder of the code executes in the next switching cycle. As shown in Figure 2-4, the period register for ePWM1 gets updated before the end of the switching cycle, while the period register for ePWM2 does not get updated on time. As a result, ePWM2 operates with the old PWM frequency, while ePWM1 operates with the new frequency, which can be disastrous for the power stage.

Figure 2-4 Potential Issue if the ISR Occurs at the Switching Cycle Boundary

In order to update the shadow registers of different ePWM modules as soon as possible, new types of ePWM provide register linking scheme, with the link register EPWMXLINK. This prevents situations where a SyncIn pulse forces a shadow to active load of these registers before all registers are updated among ePWM modules. TBPRD:TBPRDHR, CMPA:CMPAHR, CMPB:CMPBHR, CMPC, and CMPD registers can be enabled with EPWMXLINK. The corresponding register will simultaneously be written with the same value which is written to the register of the ePWM module being linked to.

With the simultaneous write feature, the same register among different ePWM modules can be ensured to be updated always at the same time. However, since different shadow registers within the same ePWM module are still required to be updated in software manually one by one, it might happen that not all the ePWM registers are updated before the shadow to active load event. One disastrous result might occur as shown in Figure 2-5.

Figure 2-5 Disastrous Result When Different Registers are not Updated Simultaneously