SPRAD00 December   2021 TDA4VM

 

  1.   Trademarks
  2. 1Introduction
  3. 2Jacinto 7 Display Subsystem Overview
    1. 2.1 Video (Input) Pipelines
    2. 2.2 Writeback Pipeline
    3. 2.3 Overlay Manager
    4. 2.4 Output Processing
    5. 2.5 Output Display Interfaces
      1. 2.5.1 Embedded Display Port (eDP)
      2. 2.5.2 MIPI Display Serial Interface (DSI)
      3. 2.5.3 Display Parallel Interface (DPI)
    6. 2.6 Safety Support
  4. 3Display Subsystem Use-case Examples
    1. 3.1 3-Display Configuration
  5. 4TDA4VM/DRA829V Hardware Display Support
  6. 5 Display Subsystem Software Architecture
    1. 5.1 Linux DSS Architecture
    2. 5.2 QNX Software Architecture
    3. 5.3 RTOS-Based DSS Support
  7. 6References

2.1 Video (Input) Pipelines

  • 4x input display pipes enable up to 4 concurrent displays
    • 2x Video pipelines and 2x Video Lite pipelines
  • Each pipe supports 10-bit width for HDR video
  • Input RGB and YUV source pixel formats
  • 4K x2K (UHD) resolution support
  • Flexible line-buffer enables >4K line width for wide/short displays (8Kx1k)
  • 2x Video Pipelines support upscaling and downscaling
    • Programmable poly-phase filter (scaler)
    • Independent horizontal and vertical re-sampling: up-sampling (up to x16) and down-sampling (down to x0.25)
  • Color Space Conversion
  • Programmable VC1 range mapping
  • Programmable Brightness/Contrast/Hue/Saturation
  • Programmable Gamma Correction LUT
  • Luma Key generation