SPRAD34B July   2023  – October 2023 MSPM0G1507

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Getting Started With MSPM0 Motor Control
  6. 3Brushed-DC Motor Control
    1. 3.1 Background
    2. 3.2 Software Architecture
    3. 3.3 Block Diagrams
      1. 3.3.1 H-Bridge Motor Driver
      2. 3.3.2 H-Bridge Gate Driver
    4. 3.4 Hardware Support
    5. 3.5 Software Support
    6. 3.6 Evaluating Brushed-DC with MSP Motor Control SDK
  7. 4Stepper Motor Control
    1. 4.1 Background
    2. 4.2 Software Architecture
    3. 4.3 Block Diagrams
    4. 4.4 Hardware Support
    5. 4.5 Software Support
    6. 4.6 Evaluating Stepper With MSP Motor Control SDK
  8. 5BLDC Sensored Trap Control
    1. 5.1 Background
    2. 5.2 Software Architecture
    3. 5.3 Block Diagrams
    4. 5.4 Hardware Support
    5. 5.5 Software Support
    6. 5.6 Evaluating Sensored Trap with MSP Motor Control
  9. 63-Phase Sensorless FOC Control
    1. 6.1 Background
    2. 6.2 Software Architecture
    3. 6.3 Block Diagrams
      1. 6.3.1 MSPM0Gx10x and Gate Driver with Analog/MOSFET Integration
      2. 6.3.2 MSPM0Gx50x Analog Integration and Gate Driver
    4. 6.4 Hardware Support
    5. 6.5 Software Support
    6. 6.6 Evaluating Sensorless FOC with MSP Motor Control
    7. 6.7 Sensorless FOC Performance
  10. 7References
  11.   Revision History

4.3 Block Diagrams

The block diagrams showcase two supported MSPM0L1xxx designs for stepper motors in the MSPM0L1xxx Stepper SDK:

  • 4-PWM control (PWM interface)
  • 1-PWM control (STEP interface)

As shown in Figure 4-4, the signals used in 4-PWM control (PWM interface) are:

  • 4 PWM signals with edge-aligned synchronization (PWM 4x)
  • 8-bit DAC reference voltage for current regulation (VREF)(1)
  • Logic-low fault signal from driver (nFAULT)
  • Gate driver shutoff signal (DRVOFF)
  • Low-power mode signal for drivers with sleep mode pin (nSLEEP)
  • ADC current sense feedback from integrated current sense to measure motor phase currents

(1) VREF available using 8-bit DAC from COMP module, available in MSPM0L130x only.

GUID-20230411-SS0I-37TK-MBG5-LL7T7XPXQKHJ-low.svg Figure 4-4 Block Diagram for 4-PWM Interface for Stepper Motor Control

As shown in Figure 4-5, the signals used in 1-PWM Control (STEP interface) are:

  • 1-PWM signal with adjustable duty cycle and pulse width (STEP)
  • Direction pin (DIR)
  • 8-bit DAC reference voltage for current regulation (VREF)
  • Logic-low fault signal from driver (nFAULT)
  • Gate driver shutoff signal (DRVOFF)
  • Low-power mode signal for drivers with sleep mode pin (nSLEEP)
  • Optional SPI read/write interface (for drivers with SPI interface)
GUID-20230411-SS0I-CQDF-1DP3-ST9HJBRWDCWD-low.svg Figure 4-5 Block Diagram for 1-PWM Interface for Stepper Motor Control