SPRUIW3 October   2021 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   Trademarks
  2. 1Feature Differences Between F28004x and F28003x
    1. 1.1 F28004x and F28003x Feature Comparison
  3. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 100-Pin PZ Package
      1. 2.1.1 100-Pin PZ Migration for Existing PCB
      2. 2.1.2 100-Pin PZ Migration for New PCB Design
    2. 2.2 PCB Hardware Changes for the 64-Pin PM Package
      1. 2.2.1 64-Pin PM Migration for New and Existing PCB
  4. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28003x
      1. 3.1.1  TMU Type1
      2. 3.1.2  Fast Integer Division (FINTDIV)
      3. 3.1.3  Host Interface Controller (HIC)
      4. 3.1.4  Background CRC (BGCRC)
      5. 3.1.5  Standby Low Power Mode
      6. 3.1.6  X1 GPIO Functionality
      7. 3.1.7  Diagnostic Features (PBIST/HWBIST)
      8. 3.1.8  Advance Encryption Standard (AES)
      9. 3.1.9  Secure Boot/JTAG Lock
      10. 3.1.10 Modular Controller Area Network (MCAN)
      11. 3.1.11 Embedded Pattern Generator (EPG)
      12. 3.1.12 Live Firmware Update (LFU)
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 XTAL Module
      2. 3.5.2 PLL
      3. 3.5.3 PIE Channel Mapping
      4. 3.5.4 Bootrom
      5. 3.5.5 CLB and Motor Control Libraries
      6. 3.5.6 ERAD
      7. 3.5.7 GPIO
      8. 3.5.8 AGPIO
      9. 3.5.9 ERROR Status
    6. 3.6 Power Management
      1. 3.6.1 LDO/VREG
      2. 3.6.2 DCDC
      3. 3.6.3 POR/BOR
      4. 3.6.4 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
    9. 3.9 Analog Multiplexing Changes
  5. 4Application Code Migration From F28004x to F28003x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 Minimum Compiler Version Requirement for TMU Type 1
    4. 4.4 C2000Ware Examples
  6. 5Specific Use Cases Related to F28003x New Features
    1. 5.1 HIC
    2. 5.2 FINTDIV
    3. 5.3 TMU Type1
    4. 5.4 AES
    5. 5.5 MCAN
    6. 5.6 EPG
  7. 6EABI Support
    1. 6.1 Flash API
    2. 6.2 NoINIT Struct Fix (Linker Command)
    3. 6.3 Pre-Compiled Libraries
  8. 7References

3.3 Control Module Changes

There are changes in the control modules between the F28004x and F28003x devices. The biggest changes come from the EPWM on the F28003x device which has a new generic and simple sync scheme that allows any EPWM/ECAP to be the main sync source for another EPWM/ECAP and addition of new SDFM features for F28003x. Table 3-2 shows the module instances differences which should be considered when migrating applications between F28004x and F28003x.

Table 3-2 Control Module Differences
Module Category F28004x F28003x Notes
SDFM Number 4 - SD1_D1C1..D4C4 8 - SD1_D1C1..D4C4, SD2_D1C1..D4C4
Registers(1) SDCMPHx SDFLTxCMPH1 High-Level Threshold Register for Chx
SDCMPLx SDFLTxCMPL1 Low-Level Threshold Register for Chx
SDCMPHZx SDFLTxCMPHZ High-Level (Z) Threshold Register for Chx
- SDFLTxCMPH2 Second High-Level Threshold Register for Chx
- SDFLTxCMPL2 Second Low-Level Threshold Register for Chx
- SDCOMPxCTL SD Comparator event filterx Control Register
- SDCOMPxEVT2FLTCTL COMPL/CEVT2 Digital filterx Control Register
- SDCOMPxEVT2FLTCLKCTL COMPL/CEVT2 Digital filterx Clock Control Register
- SDCOMPxEVT1FLTCTL COMPH/CEVT1 Digital filterx Control Register
- SDCOMPxEVT1FLTCLKCTL COMPH/CEVT1 Digital filterx Clock Control Register
- SDCOMPxLOCK SD Comparator event filterx Lock Register
eQEP Number 2 - EQEP1, EQEP2
Registers - QEPSRCSEL Select source as either device pins or cmpss/epwmxbar
- QDECCTL.QIDIRE Index direction compatibility mode
Other Support for SinCos Transducers
eCAP Number 7 - ECAP1..7 3 - ECAP1..3 Updates on F28003x due to new sync scheme
Registers - ECAPSYNCINSEL Select sync source for ecap
HRCAP Number 2 - HRCAP6, HRCAP7 1 - HRCAP3
ePWM Number 8 - EPWM1..8 Updates on F28003x due to new sync scheme and blanking window improvements
Registers - DCACTL.EVT1LATSEL DCAEVT1 Latched Signal Select
- DCACTL.EVT1LATCLRSEL DCAEVT1 Latched Clear Source Select
- DCACTL.EVT1LAT Indicates the status of DCAEVT1LAT signal
- DCACTL.EVT2LATSEL DCAEVT2 Latched Signal Select
- DCACTL.EVT2LATCLRSEL DCAEVT2 Latched Clear Source Select
- DCACTL.EVT2LAT Indicates the status of DCAEVT2LAT signal
- DCBCTL.EVT1LATSEL DCBEVT1 Latched Signal Select
- DCBCTL.EVT1LATCLRSEL DCBEVT1 Latched Clear Source Select
- DCBCTL.EVT1LAT Indicates the status of DCBEVT1LAT signal
- DCBCTL.EVT2LATSEL DCBEVT2 Latched Signal Select
- DCBCTL.EVT2LATCLRSEL DCBEVT2 Latched Clear Source Select
- DCBCTL.EVT2LAT Indicates the status of DCBEVT2LAT signal
DCFCCTL.PULSESEL DCFCCTL.PULSESEL Blank Pulse Mix added as an option for F28003x
- TBCTL3.OSSFRCEN F28003x can now generate an EPWMxSYNCO with GLDCTL2[OSHTLD]
SYNCSEL EPWMSYNCINSEL EPWMxSYNCI to EPWMxSYNCO path removed from F28003x
TBCTL.SYNCOSEL EPWMSYNCOUTEN DCAEVT1 and DCBEVT1 are new sync output options for F28003x
TBCTL2.SYNCOSELX
HRPWM Number 8 - HRPWM1..8 4 - HRPWM1..4
Clock Source EPWM1CLK Respective EPWM
  1. x = 1 to 4