SPRUJ07 august   2023 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F2837x and F28P65x
    1. 1.1 F2837x and F28P65x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 176-Pin PTP and 100-Pin PZP Package
    2. 2.2 Use of Existing 176-Pin F2837x PCB Design
      1.      9
      2. 2.2.1 JTAG TRSTn No-Connect
      3. 2.2.2 GPIO Input Buffer Control Register
      4. 2.2.3 176-Pin GPIO Pin/Multiplex and ADCD Considerations
        1. 2.2.3.1 176-Pin PTP Pins with Different GPIO Assignment
        2. 2.2.3.2 ADCD Channel Migration
    3. 2.3 176-Pin PTP New PCB Design
    4. 2.4 100-Pin PZP New PCB Design
    5. 2.5 337-BGA ZWT Application to 256-BGA ZEJ or 169-BGA NMR
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P65x
      1. 3.1.1 Lock-step Compare Module (LCM)
      2. 3.1.2 Expanded Analog Channels
      3. 3.1.3 Firmware Update (FWU)
      4. 3.1.4 Flexible GPIO and Digital Input Pins
      5. 3.1.5 ADC Hardware Redundancy Safety Checker
      6. 3.1.6 Flexible Memory Sharing between CPU Subsystems
      7. 3.1.7 Increased RAM Program Memory on CLA
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PIE Channel Mapping
        1. 3.5.1.1 F2837x vs F28P65x PIE Channel Mapping Comparison
      2. 3.5.2 Bootrom
      3. 3.5.3 AGPIO Filter
    6. 3.6 Power Management
      1. 3.6.1 VREGENZ
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
      1. 3.8.1 F2837x vs F28P65x GPIO Mux Comparison
    9. 3.9 Analog Multiplexing Changes
      1. 3.9.1 F2837x_176PTP vs F28P65x_176PTP Analog Connections Comparison
  7. 4Application Code Migration From F2837x to F28P65x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5EABI Support
    1. 5.1 NoINIT Struct Fix (Linker Command)
    2. 5.2 Pre-Compiled Libraries
  9.   References

2.2.2 GPIO Input Buffer Control Register

The GPIO input buffer control register (GPIOINENACTRL) configures whether the input buffer is enabled or disabled. Default setting is disabled. In the case where the corresponding GPIO is connected to VDD after migrating to F28P65x, the appropriate GPIO bit in this register has to be set to '1' to prevent errors when powering up the F28P65x device. This register is in the analog subsystem, which has a base address of 0x0005 D700. GPIOINENACTRL has an offset of 0x134.

Table 2-2 GPIOINENACTRL Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h Reserved
5 GPIO103 R/W 1h One time configuration for GPIO103 to decide whether Input buffer (INENA control) is enabled or disabled
0 - Input buffer is disabled
1 - Input buffer is enabled
Reset type: XRSn
4 GPIO46 R/W 1h One time configuration for GPIO46 to decide whether Input buffer (INENA control) is enabled or disabled
0 - Input buffer is disabled
1 - Input buffer is enabled
Reset type: XRSn
3 GPIO31 R/W 1h One time configuration for GPIO31 to decide whether Input buffer (INENA control) is enabled or disabled
0 - Input buffer is disabled
1 - Input buffer is enabled
Reset type: XRSn
2 GPIO25 R/W 1h One time configuration for GPIO25 to decide whether Input buffer (INENA control) is enabled or disabled
0 - Input buffer is disabled
1 - Input buffer is enabled
Reset type: XRSn
1 GPIO23 R/W 1h One time configuration for GPIO23 to decide whether Input buffer (INENA control) is enabled or disabled
0 - Input buffer is disabled
1 - Input buffer is enabled
Reset type: XRSn
0 GPIO0 R/W 1h One time configuration for GPIO0 to decide whether Input buffer (INENA control) is enabled or disabled
0 - Input buffer is disabled
1 - Input buffer is enabled
Reset type: XRSn