SPRZ412N December   2013  – May 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1

 

  1.   1
  2.   Abstract
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision C Usage Notes and Advisories
    1. 3.1 Silicon Revision C Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 SYS/BIOS: Version Implemented in Device ROM is not Maintained
      4. 3.1.4 SDFM: Use Caution While Using SDFM Under Noisy Conditions
      5. 3.1.5 McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY Bit is in its Ready State (1)
    2. 3.2 Silicon Revision C Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
      23.      Advisory
      24.      Advisory
      25.      Advisory
      26.      Advisory
      27.      Advisory
      28.      Advisory
      29.      Advisory
      30.      Advisory
      31.      Advisory
      32.      Advisory
      33.      Advisory
      34.      Advisory
      35.      Advisory
      36.      Advisory
      37.      Advisory
      38.      Advisory
  6. 4Silicon Revision B Usage Notes and Advisories
    1. 4.1 Silicon Revision B Usage Notes
    2. 4.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
  7. 5Silicon Revision A Usage Notes and Advisories
    1. 5.1 Silicon Revision A Usage Notes
    2. 5.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
  8. 6Silicon Revision 0 Usage Notes and Advisories
    1. 6.1 Silicon Revision 0 Usage Notes
    2. 6.2 Silicon Revision 0 Advisories
      1.      Advisory
  9. 7Documentation Support
  10. 8Trademarks
  11. 9Revision History

McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY Bit is in its Ready State (1)

Revisions Affected: 0, A, B, C

If the XRDY bit is used to properly gate writes to the DX2/DX1 registers, this condition will not occur.

Per the operation of the McBSP, a write to the DX1 data transmit register will automatically clear the XRDY bit, indicating a not-ready status. Once this data is transferred to the internal transmit shift register (XSR1), the McBSP HW will set the XRDY bit, indicating a ready status, and new data can be written to DX2/DX1 data transmit registers.

If the set and clear of XRDY occur on the same CPU clock cycle, the XRDY bit will remain cleared and the new data in the DX2/DX1 will not be transmitted.

In this state of XRDY = 0, the McBSP will be in the not-ready status indefinitely.

Any subsequent writes to DX2/DX1 will behave normally and the XRDY bit will function as normal.

Workarounds:

When transmitting multiple words of data using the McBSP module, poll the XRDY bit in the SPCR2 register before writing new data to the DX2/DX1 registers to prevent overwriting. For those modules that do not have access to the XRDY bit (such as the DMA controller), the XINT interrupt inside the McBSP module can be configured to reflect XRDY (through the XINTM bits in SPCR2 register), and this can also be used to gate writes to the DX2/DX1 registers. This will also ensure that the XRDY bit is not set and cleared on the same CPU cycle, causing the above “not-ready indefinitely” condition.

If the system allows multiple bus controllers, such as the C28x CPU and the DMA controller, to write to the DX2/DX1 registers, then the ready state of the XRDY bit should be validated before passing control of the McBSP to a different bus controller. This will ensure that the state of XRDY is accurate and the simultaneous set/clear action does not occur.