| FPU |
FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p
Operation |
Yes |
Yes |
Yes |
| SDFM |
SDFM: Dynamically Changing Threshold Settings (LLT, HLT),
Filter Type, or COSR Settings Will Trigger Spurious Comparator
Events |
Yes |
Yes |
Yes |
| SDFM |
SDFM: Dynamically Changing Data Filter Settings (Such as Filter
Type or DOSR) Will Trigger Spurious Data Acknowledge
Events |
Yes |
Yes |
Yes |
| SDFM |
SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields
CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock
Cycles can Corrupt SDFM State Machine, Resulting in Spurious
Comparator Events |
Yes |
Yes |
Yes |
| SDFM |
SDFM: Manchester Mode (Mode 2) Does Not Produce Correct Filter
Results Under Several Conditions |
Yes |
Yes |
Yes |
| eQEP |
eQEP: Position Counter Incorrectly Reset on Direction Change
During Index |
Yes |
Yes |
Yes |
| eQEP |
eQEP: eQEP Inputs in GPIO Asynchronous Mode |
Yes |
Yes |
Yes |
| VDD
Supply: |
VDD Supply: During VDDIO Power Up,
VDD May Also Rise |
Yes |
Yes |
Yes |
| eCAP |
eCAP: HRFRC is Not EALLOW-Protected |
Yes |
Yes |
Yes |
| PLL |
PLL: PLL May Not Lock on the First Lock Attempt |
Yes |
Yes |
Yes |
| LPM |
LPM: STANDBY Low-Power Mode is Not Supported |
Yes |
Yes |
Yes |
| DCC |
DCC: Single-Shot-Mode Operation May End
Prematurely |
Yes |
Yes |
Yes |
| BOR |
BOR: VDDIO Between 2.45 V and 3.0 V can Result in Multiple XRSn
Pulses |
Yes |
Yes |
Yes |
| I2C |
I2C: SDA and SCL Open-Drain Output Buffer Issue |
Yes |
Yes |
Yes |
| I2C |
I2C: Target Transmitter Mode, Standard Mode SDA Timings
Limitation |
Yes |
Yes |
Yes |
| ePWM |
ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the
End of the Blanking Window |
Yes |
Yes |
Yes |
| ePWM |
ePWM: Trip Events Will Not be Filtered by the Blanking Window
for the First 3 Cycles After the Start of a Blanking
Window |
Yes |
Yes |
Yes |
| ePWM |
ePWM: Event Latch (DCxEVTxLAT) of "DC Event-Based CBC Trip" May
not Extend Trigger Pulse as Expected When Asynchronous Path is
Selected |
Yes |
– |
– |
| INTOSC |
INTOSC: VDDIO Powered Without VDD Can Cause INTOSC Frequency
Drift |
Yes |
Yes |
Yes |
| FSI |
FSI: RX FIFO Spurious Overrun |
Yes |
Yes |
Yes |
|
During DCAN FIFO Mode, Received Messages May be Placed Out of
Order in the FIFO Buffer |
Yes |
Yes |
Yes |
| Boot ROM |
Boot ROM: Calling SCI Bootloader from
Application |
Yes |
Yes |
Yes |
| Boot ROM,
MPOST |
Boot-ROM, MPOST: Longer Boot Time With MPOST
Enabled |
Yes |
Yes |
Yes |
| Memory |
Memory: Prefetching Beyond Valid Memory |
Yes |
Yes |
Yes |
| SYSTEM |
SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a
System Hang |
Yes |
Yes |
Yes |
| ADC |
ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt
Mode) is not Set |
Yes |
Yes |
Yes |
| ADC |
ADC: Degraded ADC Performance With ADCCLK Fractional
Divider |
Yes |
Yes |
Yes |
| ADC |
ADC: DMA Read of Stale Result |
Yes |
Yes |
Yes |
| CLB |
CLB: Back-to-Back PUSH or PULL Instructions With More Than One
Active High Level Controller (HLC) Channel is not
Supported |
Yes |
Yes |
Yes |
| Analog
Subsystem |
Analog Subsystem: Software Configuration for Shared Reference
Pins |
Yes |
Yes |
– |
|
Analog Trim of Some TMX Devices |
Yes |
Yes |
– |
| PGA |
PGA: Output Filter Path is Not Supported |
Yes |
Yes |
– |
| ROM |
ROM: Flash API Library and FPU32 Twiddle Factor RFFT Table Not
Present |
Yes |
Yes |
– |
| REVID |
REVID: Some TMX Revision A Devices Have an Incorrect REVID
Value |
– |
Yes |
– |
| GPIO |
GPIO: X2/GPIO18 Pin Pullup Current During Power
Up |
Yes |
Yes |
Yes |
| GPIO |
GPIO: Open-Drain Configuration May Drive a Short High
Pulse |
Yes |
Yes |
Yes |
| GPIO |
GPIO: Parasitic Path to VSS When Maximum
VIH is Exceeded in Input Mode |
– |
Yes |
– |
| GPIO |
GPIO: Pins may Drive High During Power Up |
Yes |
– |
– |
| GPIO |
GPIO: Signal Latch-up to VSS |
Yes |
– |
– |
| LIN |
LIN: Inconsistent Sync Field Error (ISFE) Flag/Interrupt Not
Set When Sync Field is Erroneous |
Yes |
Yes |
Yes |