SWRA779 September   2023 CC3300 , CC3301

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Main Features
    1. 2.1 Dual Host Interface
    2. 2.2 Shared Host Interface
    3. 2.3 Autonomous Mode
    4. 2.4 Host Interrupt
      1. 2.4.1 Out-of-Band Interrupt
      2. 2.4.2 In-Band Interrupt
  6. 3Interfaces
    1. 3.1 Introduction
    2. 3.2 SDIO Interface
      1. 3.2.1 SDIO Overview
      2. 3.2.2 SDIO Flow Control
    3. 3.3 SPI Interface
      1. 3.3.1 SPI Overview
      2. 3.3.2 SPI Configuration
      3. 3.3.3 SPI Flow Control
    4. 3.4 Uart Interface
      1. 3.4.1 UART Overview
      2. 3.4.2 UART Configuration
      3. 3.4.3 UART Flow Control
    5. 3.5 Pin Count Options
  7. 4Host Communication
    1. 4.1 Protocol Overview
    2. 4.2 SDIO Wrapper
    3. 4.3 SPI Wrapper
  8. 5Boot Flow
    1. 5.1 SDIO
    2. 5.2 SPI

3.3.2 SPI Configuration

There are four modes of operation defined in the SPI standard. For communication to be successful, the controller and peripheral devices must be configured in the same way. The four modes are all combinations of SPI clock polarity and phase. Only mode 0 is supported, meaning the SPI clock is active high where data is sampled on rising edge of the clock and shifted out on falling edge of the clock.

There are few more SPI parameters that may be configured during interface initialization from the host for better compatibility and flexibility.

  • Little and big endian: both are supported. In Big Endian the least significant byte is on the wire first.
  • 16-bits and 32-bits word length: both are supported.
  • Bit swizzle: when enabled, bit swizzle reverses the bit order for each word on the wire. The only exception is during busy signals as described under the Flow Control section.

Table 3-5 illustrates the different option for data on the wire.

Table 3-5 SPI Interface Format Configuration
Format Data on Wire
16-Bit Little Endian no swizzle B1(b15 to b8) B0(b7 to b0) B3(b31 to b24) B2(b23 to b16)
16-Bit Little Endian with swizzle B0(b0 to b7) B1(b8 to b15) B2(b16 to b23) B3(b24 to b31)
16-Bit Big Endian no swizzle B0(b7 to b0) B1(b15 to b8) B2(b23 to b16) B3(b31 to b24)
16-Bit Big Endian with swizzle B1(b8 to b15) B0(b0 to b7) B3(b24 to b31) B2(b16 to b23)
32-Bit Little Endian no swizzle B3(b31 to b24) B2(b23 to b16) B1(b15 to b8) B0(b7 to b0)
32-bit Little Endian with swizzle B0(b0 to b7) B1(b8 to b15) B2(b16 to b23) B3(b24 to b31)
32-Bit Big Endian no swizzle B0(b7 to b0) B1(b15 to b8) B2(b23 to b16) B3(b31 to b24)
32-Bit Big Endian with swizzle B3(b24 to b3) B2(b16 to b23) B1(b8 to b15) B0(b0 to b7)

Configuring these characteristics is done during initialization of the host interface. Since the hardware lines of the host interface are SDIO lines by default, and since the same lines are used for SPI as well, the initial configuration of the SPI characteristics is applied using an SDIO command, CMD0 (see ‎SPI chapter).

Table 3-6 summarizes all possible configurations.

Table 3-6 SPI Interface Configuration Summary
Characteristics Supported Configuration
Clock polarity Data is sampled on the rising edge. Data is shifted out on falling edge for standard SPI and rising edge for non-standard SPI
Clock phase Clock idles at logical 0
Word size 16 or 32 bits
Host Endianity Configurable
Bit order Configurable via the bit swizzle
Chip Select polarity Active low
Host Interrupt polarity Configurable
Clock frequency Up to 26 MHz for standard mode and 52 MHz for non-standard mode
Chip select assertion between words May go high between words
Autonomous mode Supported