SWRZ092B April   2021  – March 2022 IWR6843AOP

 

  1. 1Introduction
  2. 2Device Nomenclature
  3. 3Device Markings
  4. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
  5. 5Advisory to Silicon Variant / Revision Map
  6. 6Known Design Exceptions to Functional Specifications
    1.     MSS#03
    2.     MSS#10
    3.     MSS#11
    4.     MSS#12
    5.     MSS#13
    6.     MSS#14
    7.     MSS#16
    8.     MSS#17
    9.     MSS#18
    10.     MSS#19
    11.     MSS#20
    12.     MSS#21
    13.     MSS#22
    14.     MSS#23
    15.     MSS#24
    16.     MSS#25
    17.     MSS#26
    18.     MSS#27
    19.     MSS#28
    20.     MSS#29
    21.     MSS#30
    22.     MSS#31
    23.     MSS#32
    24.     MSS#33
    25.     MSS#34
    26.     MSS#35
    27.     MSS#36
    28.     MSS#37B
    29.     MSS#38A
    30.     MSS#39
    31.     MSS#40
    32.     MSS#41
    33.     MSS#42A
    34.     MSS#43A
    35.     MSS#44A
    36.     MSS#45
    37. 6.1 MSS#50
    38. 6.2 MSS#51
    39.     ANA#11B
    40.     ANA#12A
    41.     ANA#13B
    42.     ANA#14
    43.     ANA#16
    44.     ANA#17A
    45.     ANA#18B
    46.     ANA#19
    47.     ANA#20
    48.     ANA#22A
    49. 6.3 ANA#27A
    50.     ANA#30
    51.     ANA#31
    52.     DSS#01
    53.     DSS#02
    54.     DSS#03
    55.     DSS#05
    56.     DSS#07
    57.     PACKAGE#01
    58.     PACKAGE#02
  7. 7Trademarks
  8. 8Revision History

PACKAGE#02

Surface Wave Artifact from PCB

Revisions Affected

IWR6843AOP ES1.0 and IWR6843AOP ES2.0

Description:

Large PCBs area around the E-plane causes surface waves that create large ripples in the elevation direction of the AoP antenna radiation pattern.

GUID-20210415-CA0I-QMNM-4KQB-RZL60NWR7KDN-low.png

Workaround #1

Keep the Edge of PCB close to the edge of the AoP device in the E-plane to minimize the surface wave ripples.

GUID-20210415-CA0I-VB8L-WPXZ-VBH1XNFSLJD5-low.png Figure 6-5 Small form factor board with PCB edge less than 0.3mm

Workaround #2

If a larger board is needed for the solution, a trapezoid cutout with the PCB edge less than <0.3mm from the edge of the AoP should be implemented to minimize the ripples caused by surface waves.

GUID-20210415-CA0I-8SMX-BWT8-H837KVTTFHHQ-low.png Figure 6-6 Large form factor board with trapezoidal cutout and PCB edge less than 0.3mm