SWRZ117 June   2022 CC2652PSIP

 

  1.   Abstract
  2.   Trademarks
  3. 1Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Advisories
    1.     Advisory Power_03
    2.     Advisory PKA_01
    3.     Advisory PKA_02
    4.     Advisory I2C_01
    5.     Advisory I2S_01
    6.     Advisory CPU_01
    7.     Advisory CPU_02
    8.     Advisory CPU_03
    9.     Advisory CPU_Sys_01
    10.     Advisory Sys_01
    11. 3.1 Sys_05
    12.     Advisory SYSCTRL_01
    13.     IOC_01
    14.     SRAM_01
    15.     GPTM_01
    16.     ADC_01
    17.     ADC_02
    18.     ADC_03
    19.     ADC_04
    20.     ADC_05
  6. 4Revision History

Advisory I2S_01

I2S Bus Faults are Not Reported

Revisions Affected:

Revision F

Details:

The I2S module will not set the bus error interrupt flag (I2S0.IRQFLAGS.BUS_ERR) if an I2S read or write causes a system bus fault that results from access to illegal addresses (usage error).

Workaround:

Software must ensure that memory area used by the I2S DMA is accessible, meaning that the memory is powered on and the system bus is connected..

As an example; The TI-provided SPI driver SPICC26X2DMA.c will ensure that the flash memory is kept accessible also in Idle power mode if the transmit buffer address starts with 0x0 to ensure no bus faults occur. A similar approach needs to be taken if writing a peripheral driver utilizing I2S.