DLPA078B February   2017  – September 2021 DLP160AP , DLP160CP , DLP2000 , DLP2010 , DLP230GP , DLP230KP , DLP230NP , DLP3010 , DLP3310 , DLP4710 , DLP471TP , DLPC3420 , DLPC3421

 

  1.   Trademarks
  2. 1 Introduction to Optical Modules
    1. 1.1 DLP Pico Chip or Digital Micromirror Device (DMD)
    2. 1.2 Illumination
    3. 1.3 llumination Optics
    4. 1.4 Projection Optics
    5. 1.5 Flash Memory Board
  3. 2 Use Case Considerations
    1. 2.1 Optical Module Specifications
  4. 3 Core Optical Module Specifications
    1. 3.1 Brightness
    2. 3.2 Size
    3. 3.3 Resolution
    4. 3.4 Illumination Power Consumption
    5. 3.5 Throw Ratio
    6. 3.6 Offset
    7. 3.7 Contrast Ratio
  5. 4 Additional Optical Module Specifications
    1. 4.1 Brightness Uniformity
    2. 4.2 Focus Uniformity
    3. 4.3 Color Management
    4. 4.4 Illumination Type
    5. 4.5 Thermal Management
    6. 4.6 Optical Zoom
    7. 4.7 Depth of Focus
    8. 4.8 Focus Method
    9. 4.9 Automatic White Point Correction
  6. 5 Features Implemented in Software
    1. 5.1 Keystone Correction
    2. 5.2 DLP Image Processing Settings
    3. 5.3 DLP IntelliBright Algorithms
  7. 6 Hardware Integration Considerations
    1. 6.1 Flash Memory
    2. 6.2 DLP Controller to DMD Interface
    3. 6.3 Flash Memory to DLP Controller Interface
  8. 7 Business Considerations
    1. 7.1 Cost
    2. 7.2 Custom Optical Modules
    3. 7.3 Minimum Order Quantity (MOQ)
    4. 7.4 Lead Times
  9. 8 Example Optical Module Specification Table
  10. 9 Get Started with Development
  11. 10Revision History

6.2 DLP Controller to DMD Interface

The interface between the DLPC343x controller and the DMD consists of four single ended control signals and a sub-LVDS bus consisting of 4 or 8 (depending on the DMD) data pairs and a clock pair. The differential signals make up the HS (high speed) bus that sends mirror on/off data to the DMD. Three of the four control lines (LS_CLK, LS_WDATA and LS_RDATA) make up a serial control bus. While the fourth line (ARSTZ) is a power up reset.