DLPU125 june 2023
Register address transaction timing is shown in Register Address Transaction Timing Diagram.
A register address transaction example is
shown in Register Address Transaction
Example. There can be more than one idle clock cycle between address transfers.
The address transaction table shows an address transfer of 0x00010228
.
Signal | Idle | Write low address | Idle | Write high address | Idle |
---|---|---|---|---|---|
usb_if_clock |
1 clock cycle | 1 clock cycle | |||
usb_fd(15:8) |
0x00 | 0x02 | 0x00 | 0x00 | 0x00 |
usb_fd(7:0) |
0x00 | 0x28 | 0x00 | 0x01 | 0x00 |
usb_ctrl(2:0) |
Idle | Address – “011” | Idle | Address – “011” | Idle |