SBAA491A November 2021 – April 2022 PCM5120-Q1 , PCM6120-Q1 , TLV320ADC5120 , TLV320ADC6120

6 DRE/DRC Parameters

Table 6-1 show the parameters of the DRE/DRC algorithm. Two of the parameters are controlled by writing to the device registers. The other parameters reside in the 32-bits wide coefficient memory (Book 0, Page 5, Page 6, and Page 7) of the device. During warm boot device takes the default values for the parameters in Book 0: page 5, page 6 and page 7, for overriding these parameters with the user values we need to set the bit DRE_AGC_CFG_DEF_OVR = 1 in DSP_CFG1 register (P0_R108_D2).

Table 6-1 List of DRE Parameters

DRE PARAMETER	FUNCTION/DESCRIPTION
DRE/DRC threshold (dB)	The signal level above which the DRE/DRC is inactive.
Maximum Gain (dB)	Upper limit of gain applied by DRE/DRC.
Release Time Constant (seconds)	How fast the DRE/DRC circuitry responds with a PGA gain increase when the input signal falls below DRE/DRC threshold.
Attack Time Constant (seconds)	How fast the DRE/DRC circuitry responds with a PGA gain decrease when the input signal rises above DRE/DRC threshold.
Release Hysteresis (dB)	Amount of signal-level decrease in dB past the DRE/DRC threshold that forces the DRE/DRC to increase gain and start a release.
Attack Hysteresis (dB)	Amount of signal-level increase in dB past the DRE/DRC threshold that forces the DRE/DRC to decrease gain and start an attack.
Release Debounce (samples)	The number of consecutive input samples that falls below the DRE threshold after an attack event before the DRE/DRC starts a release and increases the PGA gain.
Attack Debounce (samples)	The number of consecutive input samples that rises above the DRE threshold after a release event before the DRE/DRC starts an attack and decreases the PGA gain.

DRE/DRC threshold: The signal level above which the DRE/DRC stops modifying the PGA and sets it to unity gain. The threshold level is expressed relative to full scale (dBFS) of the ADC output. Table 6-2 lists the DRE/DRC threshold configuration settings. The default is -54 dB. Setting a high threshold level reduces the headroom available for the DRE/DRC to react when there is a sudden increase in the signal level and can result in digital clipping and PGA saturation. Therefore, the DRE/DRC threshold has to be set with enough margin to prevent clipping with large dynamic changes in input levels.

Table 6-2 DRE/DRC Trigger Threshold Level Programmable Settings

P0_R109_D[7:4] : DRE_LVL[3:0]	DRE TRIGGER THRESHOLD LEVEL
0000	The DRE/DRC target threshold is the –12 dB output signal level.
0001	The DRE/DRC target threshold is the –18 dB output signal level.
0010	The DRE/DRC target threshold is the –24 dB output signal level.
…	…
0111 (default)	The DRE/DRC target threshold is the –54 dB output signal level.
…	…
1001	The DRE/DRC target threshold is the –66 dB output signal level.
1010 to 1111	Reserved (do no use these settings)

Maximum Gain: The maximum gain represents the upper limit of gain applied by the DRE/DRC for signals below the DRE/DRC threshold. Table 6-3 lists the Maximum Gain configuration settings. The default value is 24 dB. It can be programmed from 2 dB to 30 dB with steps of 2 dB.

Table 6-3 DRE/DRC Maximum Gain Programmable Settings

P0_R109_D[3:0] : DRE_MAXGAIN[3:0]	DRE/DRC MAXIMUM GAIN ALLOWED
0000	The DRE/DRC maximum gain allowed is 2 dB.
0001	The DRE/DRC maximum gain allowed is 4 dB.
0010	The DRE/DRC maximum gain allowed is 6 dB.
…	…
1011 (default)	The DRE/DRC maximum gain allowed is 24 dB.
…	…
1110	The DRE/DRC maximum gain allowed is 30 dB.
1111	Reserved (do not use this setting)

Release Time Constant: How fast the DRE/DRC circuitry increases the PGA gain when the input signal falls below the DRE/DRC threshold. The Release Time Constant is controlled by two coefficients:DRE_REL_ALPHA and DRE_REL_BETA. Equation 5 and Equation 6 show how to compute the DRE_REL_ALPHA and DRE_REL_BETA parameters from the following time constant.

Equation 5. DRE_REL_ALPHA = round(2³¹ * e –^{ln(9) / 48000*RT})

Equation 6. DRE_REL_BETA = (2³¹ – round(2³¹ * e –^{ln(9) / 48000*RT})

where

RT is the Release Time Constant in seconds
FSYNC is the sample rate of the ADC in Hz

Table 6-4 shows the registers that control the DRE_REL_ALPHA and DRE_REL_BETA parameters. Theses parameters are each 32-bits wide, and have to be written in 2s-complement representation. The default values for DRE_REL_ALPHA and DRE_REL_BETA corresponds to a time constant of 20 milliseconds.

Table 6-4 Programmable Registers for Release Time Constant Parameter

COEFFICIENT	PAGE	REGISTER	RESET VALUE	DESCRIPTION
DRE_REL_ALPHA	0x05	0x7C	0x7F	DRE_REL_ALPHA Byte[31:24]
	0x05	0x7D	0xB5	DRE_REL_ALPHA Byte[23:16]
	0x05	0x7E	0x16	DRE_REL_ALPHA Byte[15:8]
	0x05	0x7F	0x50	DRE_REL_ALPHA Byte[7:0]
DRE_REL_BETA	0x06	0x08	0x00	DRE_REL_BETA Byte[31:24]
	0x06	0x09	0x4A	DRE_REL_BETA Byte[23:16]
	0x06	0x0A	0xE9	DRE_REL_BETA Byte[15:8]
	0x06	0x0B	0xB0	DRE_REL_BETA Byte[7:0]

Attack Time Constant: How fast the DRE/DRC circuitry decreases the PGA gain when input signal rises above the DRE/DRC threshold. The Attack Time Constant is controlled by two coefficients: DRE_ATT_ALPHA and DRE_ATT_BETA. Equation 7 and Equation 8 show how to compute the DRE_ATT_ALPHA and DRE_ATT_BETA parameters from the following time constant.

Equation 7. DRE_ATT_ALPHA = round(2³¹ * e –^{ln(9) / 48000*AT})

Equation 8. DRE_ATT_BETA = (2³¹ – round(2³¹ * e –^{ln(9) / 48000*AT})

where

AT is the Attack Time Constant in seconds
FSYNC is the sample rate of the ADC in Hz

DRE_ATT_ALPHA and DRE_ATT_BETA coefficients are each 32-bits wide, 2s-complement representations. Table 6-5 shows the registers that control DRE_ATT_ALPHA and DRE_ATT_BETA parameters. The default values for DRE_ATT_ALPHA and DRE_ATT_BETA corresponds to a time constant of 0.1 milliseconds.

Table 6-5 Programmable Registers for Attack Time Constant Parameter

COEFFICIENT	PAGE	REGISTER	RESET VALUE	DESCRIPTION
DRE_ATT_ALPHA	0x06	0x0C	0x50	DRE_ATT_ALPHA Byte[31:24]
	0x06	0x0D	0xFC	DRE_ATT_ALPHA Byte[23:16]
	0x06	0x0E	0x64	DRE_ATT_ALPHA Byte[15:8]
	0x06	0x0F	0x5C	DRE_ATT_ALPHA Byte[7:0]
DRE_ATT_BETA	0x06	0x10	0x2F	DRE_ATT_BETA Byte[31:24]
	0x06	0x11	0x03	DRE_ATT_BETA Byte[23:16]
	0x06	0x12	0x9B	DRE_ATT_BETA Byte[15:8]
	0x06	0x13	0xA4	DRE_ATT_BETA Byte[7:0]

Release Hysteresis: Amount of signal-level decrease past the DRE/DRC threshold that forces the DRE/DRC to increase gain and start a release. Release Hysteresis is specified in dB. Equation 9 shows the computation of the DRE_REL_HYST parameter.

Equation 9. DRE_REL_HYST = round(2⁸ * RH)

where

RH (>= 0) is the Release Hysteresis in dB

The default value of DRE_REL_HYST is 0x00000300, which corresponds to a hysteresis of 3 dB. Table 6-6 shows the registers that control the DRE_REL_HYST parameter.

Table 6-6 Programmable Registers for Release Hysteresis Parameter

COEFFICIENT	PAGE	REGISTER	RESET VALUE	DESCRIPTION
DRE_REL_HYST	0x06	0x34	0x00	DRE_REL_HYST Byte[31:24]
	0x06	0x35	0x00	DRE_REL_HYST Byte[23:16]
	0x06	0x36	0x03	DRE_REL_HYST Byte[15:8]
	0x06	0x37	0x00	DRE_REL_HYST Byte[7:0]

Attack Hysteresis: Amount of signal-level increase past DRE threshold that forces the DRE/DRC to decrease the gain and start an attack. Equation 10 shows the computation of the DRE_ATT_HYST parameter.

Equation 10. DRE_ATT_HYST = round(2⁸ * AH)

where

AH (>= 0) is the Attack Hysteresis in dB

The default value of Attack Hysteresis is 1 dB. The default can be changed by writing to the registers listed in Table 6-7.

Table 6-7 Programmable Registers for Attack Hysteresis Parameter

COEFFICIENT	PAGE	REGISTER	RESET VALUE	DESCRIPTION
DRE_ATT_HYST	0x06	0x3C	0x00	DRE_ATT_HYST Byte[31:24]
	0x06	0x3D	0x00	DRE_ATT_HYST Byte[23:16]
	0x06	0x3E	0x01	DRE_ATT_HYST Byte[15:8]
	0x06	0x3F	0x00	DRE_ATT_HYST Byte[7:0]

Attack Debounce: The number of consecutive input samples that rises above the DRE/DRC threshold after a release event before the DRE/DRC starts attack and decreases the PGA. The default value of this parameter is 2 samples at 48 kHz (0.01 milliseconds). Equation 11 shows the computation of DRE_ATT_CNT parameter.

Equation 11. DRE_ATT_CNT = round(2⁸ * FSYNC * AD)

where

AD (>= 0) is specified in seconds
FSYNC is the sample rate of the ADC in Hz

Table 6-8 shows the registers controlling the DRE_ATT_CNT parameter.

Table 6-8 Programmable Registers for Attack Debounce Parameter

COEFFICIENT	PAGE	REGISTER	RESET VALUE	DESCRIPTION
DRE_ATT_CNT	0x06	0x18	0x00	DRE_ATT_CNT Byte[31:24]
	0x06	0x19	0x00	DRE_ATT_CNT Byte[23:16]
	0x06	0x1A	0x02	DRE_ATT_CNT Byte[15:8]
	0x06	0x1B	0x00	DRE_ATT_CNT Byte[7:0]

Release Debounce: The number of consecutive input samples that falls below DRE/DRC threshold after an attack event before the DRE/DRC starts releasing and increasing the PGA. The default value of Release Debounce is 25 milliseconds at 48 kHz. Equation 12 shows the computation of the DRE_REL_CNT parameter.

Equation 12. DRE_REL_CNT = round(2⁸ * FSYNC * RD)

where

RD (>= 0) is the Release Debounce specified in seconds
FSYNC is the sample rate of the ADC in Hz

Table 6-9 lists the registers controlling the DRE_REL_CNT parameter.

Table 6-9 Programmable Registers for Release Debounce Parameter

COEFFICIENT	PAGE	REGISTER	RESET VALUE	DESCRIPTION
DRE_REL_CNT	0x06	0x1C	0x00	DRE_REL_CNT Byte[31:24]
	0x06	0x1D	0x04	DRE_REL_CNT Byte[23:16]
	0x06	0x1E	0xB0	DRE_REL_CNT Byte[15:8]
	0x06	0x1F	0x00	DRE_REL_CNT Byte[7:0]