SBAS837B August   2018  – April 2020 AMC1035

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Application Example
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Modulator
      3. 7.3.3 Reference Output
      4. 7.3.4 Clock Input
      5. 7.3.5 Digital Output
      6. 7.3.6 Manchester Coding Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Behavior in Case of a Full-Scale Input
      2. 7.4.2 Fail-Safe Output
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Digital Filter Usage
    2. 8.2 Typical Applications
      1. 8.2.1 Voltage Sensing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 IGBT Temperature Sensing
      3. 8.2.3 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fCLKIN CLKIN clock frequency MCE = 0 9 20 21 MHz
MCE = 1 9 10 11
DutyCycle CLKIN clock duty cycle(1) 40% 50% 60%
tH1 DOUT hold time after rising edge of CLKIN MCE = 0, CLOAD = 15 pF 6 ns
tH2 DOUT hold time after rising edge of CLKIN MCE = 1, CLOAD = 15 pF 6 23 ns
tH3 DOUT hold time after falling edge of CLKIN MCE = 1, CLOAD = 15 pF 10 26 ns
tD1 Rising edge of CLKIN to DOUT valid delay MCE = 0, CLOAD = 15 pF 25 ns
tD2 Rising edge of CLKIN to DOUT valid delay MCE = 1, CLOAD = 15 pF 11 27 ns
tD3 Falling edge of CLKIN to DOUT valid delay MCE = 1, CLOAD = 15 pF 15 30 ns
tr DOUT rise time 10% to 90%, 3.0 V ≤ VDD ≤ 3.6 V, CLOAD = 15 pF 2.5 5 ns
10% to 90%, 4.5 V ≤ VDD ≤ 5.5 V, CLOAD = 15 pF 1.5 3.5
tf DOUT fall time 90% to 10%, 3.0 V ≤ VDD ≤ 3.6 V, CLOAD = 15 pF 2.5 5.8 ns
90% to 10%, 4.5 V ≤ VDD ≤ 5.5 V, CLOAD = 15 pF 1.8 4.4
tASTART Analog startup time VDD step to 3.0 V, 0.1% settling, CLKIN applied 0.25 ms
(1) The duty cycle of DOUT equals the clock duty cycle of the applied CLKIN signal.
AMC1035 tim_AMC1035.gifFigure 1. Digital Interface Timing
AMC1035 tim_start_bas837.gifFigure 2. Device Startup Timing