SBOS780C Data sheet

SBOS780C March 2016 – June 2021 THS3215

PRODUCTION DATA

6.5 Electrical Characteristics: D2S

at +V_CC = 6.0 V, –V_CC = –6.0 V, A_V = 2 V/V, 25-Ω source impedance, input common-mode voltage (V_IC) = 0.25 V, external OPS input selected (PATHSEL ≥ 1.3 V), V_REF = GND, R_LOAD = 100 Ω, and T_J ≈ 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT	TEST LEVEL ⁽¹⁾
AC PERFORMANCE (Power Stage Disabled: DISABLE pin ≥ 1.3 V) ⁽⁵⁾
	Small-signal bandwidth (SSBW)	V_OUT = 250 mV_PP, peaking < 1.0 dB		450		MHz	C
	Large-signal bandwidth (LSBW)	V_OUT = 2 V_PP		350		MHz	C
	Bandwidth for 0.2-dB flatness	V_OUT = 2 V_PP		65		MHz	C
	Slew rate⁽²⁾	V_OUT = 4-V step		1500		V/µs	C
	Overshoot and undershoot	Input t_r = 1 ns, V_OUT = 2-V step		2%			C
	Rise and fall time	Input t_r = 1 ns, V_OUT = 2-V step		1.2		ns	C
	Settling time to 0.1%	Input t_r = 1 ns, V_OUT = 2-V step		5		ns	C
	2nd-order harmonic distortion (HD2)	f = 20 MHz, V_OUT = 2 V_PP		–72		dBc	C
	3rd-order harmonic distortion (HD3)	f = 20 MHz, V_OUT = 2 V_PP		–88		dBc	C
	Output voltage noise	f > 200 kHz		12		nV/√ Hz	C
	Input current noise (each input)	f > 200 kHz		2.0		pA/√ Hz	C
	Output impedance	f = 20 MHz		0.9		Ω	C
DC PERFORMANCE ⁽⁵⁾
	Differential to single-ended gain	±100-mV output	1.975	2.0	2.025	V/V	A
	Differential to single-ended gain drift	T_J = –40°C to +125°C		37	43	ppm/°C	B
	VREF input pin gain	Differential inputs = 0 V, V_REF = ±100 mV	0.975	1.0	1.015	V/V	A
	VREF input pin gain drift	T_J = –40°C to +125°C		–67	–74	ppm/°C	B
	Output offset voltage	T_J ≈ 25°C	–35	±8	35	mV	A
		T_J = 0°C to 70°C	–37		36	mV	B
		T_J = –40°C to +125°C	–39		38	mV	B
	Output offset voltage drift	T_J = –40°C to +125°C	–4	–25	–45	µV/°C	B
	Input bias current – each input⁽³⁾	T_J ≈ 25°C	–4	±2	4	µA	A
		T_J = 0°C to 70°C	–4.2		4.3	µA	B
		T_J = –40°C to +125°C	–4.3		4.5	µA	B
	Input bias current drift	T_J = –40°C to +125°C	3	4	5	nA/°C	B
	Input offset current	T_J ≈ 25°C	–400	±50	400	nA	A
		T_J = 0°C to 70°C	–475		535	nA	B
		T_J = –40°C to +125°C	–595		700	nA	B
	Input offset current drift	T_J = –40°C to +125°C	–3	0.2	3	nA/°C	B
INPUTS⁽⁴⁾
	Common-mode input negative supply headroom	T_J ≈ 25°C		1.8	1.9	V	A
	Common-mode input negative supply headroom	T_J = –40°C to +85°C			2.0	V	B
	Common-mode input positive supply headroom	T_J ≈ 25°C		1.3	1.4	V	A
	Common-mode input positive supply headroom	T_J = –40°C to +125°C			1.5	V	B
	Common-mode rejection ratio (CMRR)	–1 V ≤ V_IC ≤ 3 V	42	48		dB	A
	Input impedance differential mode	V_CM = 0 V		20 \|\| 2.3		kΩ \|\| pF	C
	Input impedance common mode	V_CM = 0 V		20 \|\| 2.3		kΩ \|\| pF	C
OUTPUT⁽⁶⁾
	Output voltage headroom to either supply	T_J ≈ 25°C	1.4	1.5	1.75	V	A
	Output voltage headroom to either supply	T_J = –40°C to +85°C			1.95	V	B
	Output current drive	±0.8 V_PP, R_LOAD = 20 Ω	±35	±45		mA	A
	DC output impedance	Load current = ±20 mA		0.3		Ω	C
POWER SUPPLY (D2S + Midsupply Buffer Only; OPS Disabled: DISABLE pin ≥ 1.3 V)
	Supply current	±6-V supplies	20.2	21.3	26	mA	A
	Supply current temperature coefficient			8		µA/°C	C
	Positive power-supply rejection ratio (+PSRR)	Referred to input	62	71		dB	A
	Negative power-supply rejection ratio (–PSRR)	Referred to input	61	71		dB	A

(1) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A≈ T_J≈ 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information. DC limits tested with no self-heating. Add internal self heating to T_A for T_J.

(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √ 2) × 2π × f_–3dB.

(3) Currents out of pin treated as a positive polarity.

(4) Applies to input pins 2 (IN+) and 3 (IN–).

(5) Output measured at pin 6.

(6) Output measured at pin 6.