SCPS193D July   2010  – January 2023 TCA6424A

PRODUCTION DATA  

  1. Features
  2. Description
  3. Revision History
  4. Description (continued)
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Voltage Translation
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 I2C Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Address
    5. 8.5 Programming
      1. 8.5.1 Power-On Reset
      2. 8.5.2 Reset Input ( RESET)
      3. 8.5.3 Interrupt Output ( INT)
      4. 8.5.4 Bus Transactions
        1. 8.5.4.1 Writes
        2. 8.5.4.2 Reads
    6. 8.6 Register Maps
      1. 8.6.1 Control Register and Command Byte
      2. 8.6.2 Register Descriptions
  9. Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Detailed Design Procedure
        1. 9.1.1.1 Minimizing ICC When I/Os Control LEDs
    2. 9.2 Power Supply Recommendation
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
      1.      Mechanical, Packaging, and Orderable Information

I2C Interface

The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

I2C communication with this device is initiated by a controller sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high (see Figure 8-3). After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/ W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the target device must not be changed between the Start and the Stop conditions.

On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 8-4).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the controller (see Figure 8-3).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 8-5). When a target receiver is addressed, it must generate an ACK after each byte is received. Similarly, the controller must generate an ACK after each byte that it receives from the target transmitter. Setup and hold times must be met to ensure proper operation.

A controller receiver signals an end of data to the target transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the target. This is done by the controller receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the controller to generate a Stop condition.

GUID-199E39CF-3DC5-44C1-8A7F-D845B069FC40-low.gifFigure 8-3 Definition of Start and Stop Conditions
GUID-47DE4C7F-C226-4B0C-9330-B5FC1216781F-low.gifFigure 8-4 Bit Transfer
Figure 8-5 Acknowledgment on the I2C Bus
Table 8-2 Interface Definition
BYTEBIT
7 (MSB)6543210 (LSB)
I2C target addressLHLLLHADDRR/ W
I/O data busP07P06P05P04P03P02P01P00
P17P16P15P14P13P12P11P10
P27P26P25P24P23P22P21P20