SFFS209 September 2021 TLV6703

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TLV6703. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to Ground (see Table 4-2)
Pin open-circuited (see Table 4-3)
Pin short-circuited to an adjacent pin (see Table 4-4)
Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality
B	No device damage, but loss of functionality
C	No device damage, but performance degradation
D	No device damage, no impact to functionality or performance

Figure 4-1 shows the TLV6703 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TLV6703 data sheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

Each pin is assesed individually
All other pins are configured correctly for device functionality
DSE Package pinout used for Pin No.

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
GND	1	No change if same node as GND	D
VDD	2	Main supply shorted out (no power to device)	B
GND	3	No change if same node as GND	D
SENSE	4	Output goes low, if other input is positive	B
GND	5	No change if same node as GND	D
OUT	6	No change if GND pin is GND node	B

Table 4-3 Pin FMA for Device Pins Open-Circuited

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
GND	1	No effect	D
VDD	2	Main suppy open (no power to device)	B
GND	3	No effect	D
SENSE	4	Output my be high or low	B
GND	5	Lowest voltage pin will drive GND pin internally (via diode)	A
OUT	6	Output cannot drive application load	B

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin

Pin Name	Pin No.	Shorted to	Description of Potential Failure Effect(s)	Failure Effect Class
GND to VDD	1	2	Thermal stress due to high power dissipation	A
VDD to GND	2	3	No effect	D
GND to SENSE	3	4	No effect	D
SENSE to GND	4	5	Output goes low	B
GND to OUT	5	6	No change if GND pin is GND node	B
OUT to GND	6	1	No change if GND pin is GND node	B

Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
GND	1	Thermal stress due to high power dissipation	A
VDD	2	No change if same node as VDD	D
GND	3	No effect	D
SENSE	4	Output goes high	B
GND	5	Main supply shorted out (no power to device)	B
OUT	6	Thermal stress due to high power dissipation	A