SFFS556 March   2023 ADS1114-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 VSSOP Package
    2. 2.2 UQFN Package
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 VSSOP Package
    2. 4.2 UQFN Package

Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the ADS1114-Q1 (VSSOP and UQFN packages). The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-2 through Table 4-9 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
Class Failure Effects
A Potential device damage that affects functionality.
B No device damage, but loss of functionality.
C No device damage, but performance degradation.
D No device damage, no impact to functionality or performance.

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • RC filters on every analog input, AINx. Series resistors are sized to limit the input currents into the analog inputs to <10 mA in all circumstances (for example, if the device is unpowered and an input signal is applied).
  • External pullup resistors on the SDA, SCL, and ALERT/RDY pins to VDD.
  • External pulldown resistor on the ADDR pin to GND (I2C address = 48h) or a pullup resistor to VDD (I2C address = 49h). Other I2C address configurations are not considered.
  • NC pins are left unconnected.
  • The device is the only target on the I2C bus.