SFFS757 February   2024 DLP4620S-Q1 , DLPC231S-Q1

 

  1.   1
  2. 1Introduction
    1.     Trademarks
  3. 2 DLP4620S-Q1 Chipset Functional Safety Capability
  4. 3Development Process for Management of Systematic Faults
    1. 3.1 TI New-Product Development Process
    2. 3.2 TI Functional Safety Development Process
  5. 4 DLP4620S-Q1 Chipset Overview
    1. 4.1 Targeted Applications
    2. 4.2 DLP4620S-Q1 Chipset Functional Safety Concept
      1. 4.2.1 Typical Hazards
      2. 4.2.2 Chipset Architecture
      3. 4.2.3 Built-In Self Tests
    3. 4.3 Functional Safety Constraints and Assumptions
  6. 5Description of Hardware Component Parts
    1. 5.1 Description of System Level Built In Self Test (BISTs)
  7. 6Management of Random Faults
    1. 6.1 Fault Reporting
      1. 6.1.1 HOST_IRQ
      2. 6.1.2 Error History
      3. 6.1.3 Fault Handling
    2. 6.2 Functional Safety Mechanism Categories
    3. 6.3 Description of Functional Safety Mechanisms
      1. 6.3.1 Video Path Protection
        1. 6.3.1.1 Video Input BISTs
        2. 6.3.1.2 Video Processing BISTs
        3. 6.3.1.3 Video Output BISTs
      2. 6.3.2 Illumination Control Protection
        1. 6.3.2.1 Communication Interface and Register Protection
        2. 6.3.2.2 LED Control Feedback Loop Protection
        3. 6.3.2.3 Data Load and Transfer Protection
        4. 6.3.2.4 Watchdogs and Clock Monitors
        5. 6.3.2.5 Voltage Monitors
  8.   A Summary of Recommended Functional Safety Mechanism Usage
  9.   B Distributed Developments
    1.     B.1 How the Functional Safety Lifecycle Applies to TI Functional Safety Products
    2.     B.2 Activities Performed by Texas Instruments
    3.     B.3 Information Provided
  10.   C Revision History

6.3.2.5 Voltage Monitors

The following voltage monitors are used to make sure that the device operating voltages of the chipset are within an acceptable range

  • [SM_33] TPS99000S-Q1 DLPC231S-Q1 Real-Time Voltage Monitors:: The TPS99000S-Q1 monitors the 1.1V, 1.8V, and 3.3V power supplies to the DLPC231S-Q1. These voltages are not generated by the TPS99000S-Q1. If any these voltages drop below the thresholds specified in the TPS99000S-Q1 datasheet, the TPS99000S-Q1 asserts the PARK_Z signal low. This initiates a hardware park routine within the DLPC231S-Q1, meaning no software is executed in order for this routine to execute. The hardware park routine disables LEDs and video output to the DMD. After the routine is completed, the TPS99000S-Q1 asserts RESET_Z low, which puts the DLPC231S-Q1 into reset.
  • [SM_34] TPS99000S-Q1 DMD Voltage Monitors:The TPS99000S-Q1 generates and monitors the DMD VOFFSET, VBIAS, and VRESET voltages. Hardware monitors within the TPS99000S-Q1 detect if these voltages are outside the acceptable range and assert the PARK_Z signal low. This initiates a hardware park routine within the DLPC231S-Q1, meaning no software is executed in order for this routine to execute. The hardware park routine disables LEDs and video output to the DMD. After the routine is completed, the TPS99000S-Q1 asserts RESET_Z low, which puts the DLPC231S-Q1 into reset.
  • [SM_35] TPS99000S-Q1 Input Voltage Monitor: The TPS99000S-Q1 monitors the VMAIN input to the system via a voltage divider, AVDD 3.3V input to the TPS99000S-Q1, and the nominal 6V inputs to the TPS99000S-Q1 (VIN_DRST, VIN_LDOT_5V, VIN_LDOA_3P3V, VIN_LDOT_3P3V, DRVR_PWR). If any of these voltages drops below the threshold, the TPS99000S-Q1 asserts PARK_Z signal low. This initiates a hardware park routine within the DLPC231S-Q1, meaning no software is executed in order for this routine to execute. The hardware park routine disables LEDs and video output to the DMD. After the routine is completed, the TPS99000S-Q1 asserts RESET_Z low, which puts the DLPC231S-Q1 into reset.
  • [SM_36] TPS99000S-Q1 Internally Generated Voltage Monitors:The TPS99000S-Q1 generates and monitors several internally generated voltages (3V for ADCs and TIAs, and -8V for the photo-diode reverse biasing). Hardware monitors within the TPS99000S-Q1 detect if these voltages are outside the acceptable range and assert the PARK_Z signal low. This initiates a hardware park routine within the DLPC231S-Q1, meaning no software is executed in order for this routine to execute. The hardware park routine disables LEDs and video output to the DMD. After the routine is completed, the TPS99000S-Q1 asserts RESET_Z low, which puts the DLPC231S-Q1 into reset.
  • [SM_37] DLPC231S-Q1 DMD Voltage Monitor: Every video frame the main application takes ADC measurements of the DMD voltages—VOFFSET, VBIAS, and VRESET. If these are not within the acceptable range, and error is logged and emergency shutdown is executed.
  • [SM_38] DLPC231S-Q1 System Voltage Monitor: Every video frame the main application takes ADC measurements of several system voltages. These include the DLPC231S-Q1 voltages (P1P1V, P1P8V, P3P3V), TPS99000S-Q1 voltages (DVDD, ADC_VREF, LDOT_M8, DRVR_PWR), and VMAIN. The thresholds for VMAIN are flash configurable. Upon failure, an error is logged.