SFFS799 March   2024 TLV365-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 SOT-23 Package
    2. 2.2 SOIC Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 SOT-23 Package
    2. 4.2 SOIC Package

Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the TLVx365-Q1 (SOT-23 and SOIC packages). The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-2 through Table 4-9 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • Total supply voltage of 5V with V+ connected to 5V and V- connected to ground.
  • Input and output pins biased to 2.5V reference point.
  • Device is configured with feedback network in gain greater than or equal to 1V/V.